From: Michael Nolan Date: Wed, 13 May 2020 14:22:17 +0000 (-0400) Subject: Change FU of all shift and rotate instructions to SHIFT_ROT X-Git-Tag: convert-csv-opcode-to-binary~2668 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ced351c57a207e733bc8c95c923cbfe91d31831;p=libreriscv.git Change FU of all shift and rotate instructions to SHIFT_ROT --- diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv index 133826022..851e51238 100644 --- a/openpower/isatables/major.csv +++ b/openpower/isatables/major.csv @@ -20,9 +20,9 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 7,ALU,OP_MUL_L64,RA,CONST_SI,NONE,RT,0,1,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli,D 24,ALU,OP_OR,NONE,CONST_UI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori,D 25,ALU,OP_OR,NONE,CONST_UI_HI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris,D -20,ALU,OP_RLC,RA,CONST_SH32,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi,M -21,ALU,OP_RLC,NONE,CONST_SH32,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm,M -23,ALU,OP_RLC,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm,M +20,SHIFT_ROT,OP_RLC,RA,CONST_SH32,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi,M +21,SHIFT_ROT,OP_RLC,NONE,CONST_SH32,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm,M +23,SHIFT_ROT,OP_RLC,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm,M 38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC,0,1,stb,D 39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is1B,0,0,1,0,0,0,RC,0,1,stbu,D 44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth,D diff --git a/openpower/isatables/minor_30.csv b/openpower/isatables/minor_30.csv index 960913dc7..c1e5b8a59 100644 --- a/openpower/isatables/minor_30.csv +++ b/openpower/isatables/minor_30.csv @@ -1,11 +1,11 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form -0b0100,ALU,OP_RLC,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD -0b0101,ALU,OP_RLC,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD -0b0000,ALU,OP_RLCL,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS -0b0001,ALU,OP_RLCL,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS -0b0010,ALU,OP_RLCR,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD -0b0011,ALU,OP_RLCR,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD -0b0110,ALU,OP_RLC,RA,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD -0b0111,ALU,OP_RLC,RA,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD -0b1000,ALU,OP_RLCL,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcl,MD -0b1001,ALU,OP_RLCR,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcr,MD +0b0100,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD +0b0101,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD +0b0000,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS +0b0001,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS +0b0010,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD +0b0011,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD +0b0110,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD +0b0111,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD +0b1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcl,MD +0b1001,SHIFT_ROT,OP_RLCR,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcr,MD diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv index cd7171dff..f0cef26de 100644 --- a/openpower/isatables/minor_31.csv +++ b/openpower/isatables/minor_31.csv @@ -136,15 +136,15 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 0b0010111010,ALU,OP_PRTY,NONE,NONE,RS,RA,0,0,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,prtyd,X 0b0010011010,ALU,OP_PRTY,NONE,NONE,RS,RA,0,0,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,prtyw,X 0b0010000000,,,,,,,,,,,,,,,,,,,,,,,setb,VX -0b0000011011,ALU,OP_SHL,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,sld,X -0b0000011000,ALU,OP_SHL,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,slw,X -0b1100011010,ALU,OP_SHR,NONE,RB,RS,RA,0,0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,srad,X -0b1100111010,ALU,OP_SHR,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,sradi,XS -0b1100111011,ALU,OP_SHR,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,sradi,XS -0b1100011000,ALU,OP_SHR,NONE,RB,RS,RA,0,0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC,0,0,sraw,X -0b1100111000,ALU,OP_SHR,NONE,CONST_SH32,RS,RA,0,0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC,0,0,srawi,X -0b1000011011,ALU,OP_SHR,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,srd,X -0b1000011000,ALU,OP_SHR,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,srw,X +0b0000011011,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,sld,X +0b0000011000,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,slw,X +0b1100011010,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,0,0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,srad,X +0b1100111010,SHIFT_ROT,OP_SHR,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,sradi,XS +0b1100111011,SHIFT_ROT,OP_SHR,NONE,CONST_SH,RS,RA,0,0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,sradi,XS +0b1100011000,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,0,0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC,0,0,sraw,X +0b1100111000,SHIFT_ROT,OP_SHR,NONE,CONST_SH32,RS,RA,0,0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC,0,0,srawi,X +0b1000011011,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,srd,X +0b1000011000,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,srw,X 0b1010110110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,0,0,0,0,ZERO,0,is1B,0,0,0,1,0,0,RC,0,1,stbcx,X 0b0011110111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,0,0,0,0,ZERO,0,is1B,0,0,1,0,0,0,RC,0,1,stbux,X 0b0011010111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,0,0,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC,0,1,stbx,X