From: lkcl Date: Wed, 30 Mar 2022 10:20:56 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2950 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7cee514b9c154b093b95655cf9c1b98550a607f2;p=libreriscv.git --- diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 70456550d..fd93c4fbc 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -167,7 +167,8 @@ Normally the progression of the SV for-loop would move on to the next register. Instead however in the scalar case these instructions **remain in the same register** and insert or transfer between **bits** of the scalar integer source or destination. Further useful violation of the normal SV Elwidth override rules allows -for packing of multiple CR test results into an Integer Element. Note +for packing (or unpacking) of multiple CR test results into +(or out of) an Integer Element. Note that the CR (source operand) elwidth field is utilised to determine the bit- packing size (1/2/4/8 with remaining bits within the Integer element set to zero) whilst the INT (dest operand) elwidth field still sets