From: lkcl <lkcl@web>
Date: Wed, 19 Apr 2023 20:43:32 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7cf56d8e32f7e1b745af9332260f18a21c9264e4;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls013.mdwn b/openpower/sv/rfc/ls013.mdwn
index 56058b174..573d2cdfd 100644
--- a/openpower/sv/rfc/ls013.mdwn
+++ b/openpower/sv/rfc/ls013.mdwn
@@ -208,6 +208,23 @@ Assembly Aliases: see
 These are signed and unsigned, min or max.  SVP64 Prefixing defines Saturation
 semantics therefore Saturated variants of these instructions need not be proposed.
 
+## Integer MinMax Mode
+
+* bit 0: set if word variant else dword
+* bit 1: set if signed else unsigned
+* bit 2: set if max else min
+
+| `IMM` | Assembly Alias     |
+|-------|--------------------|
+| 000   | minu RT,RA,RB      |
+| 001   | maxu RT,RA,RB      |           
+| 010   | mins RT,RA,RB      |
+| 011   | maxs RT,RA,RB      |           
+| 100   | minuw RT,RA,RB      |
+| 101  | maxuw RT,RA,RB      |           
+| 110   | minsw RT,RA,RB      |
+| 111   | maxsw RT,RA,RB      |    
+       
 ## Minimum Unsigned
 
 X-Form