From: Henri Verbeet <hverbeet@gmail.com>
Date: Tue, 16 Nov 2010 23:29:02 +0000 (+0100)
Subject: r600g: Swizzle vertex data only once.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d0f45563d5426f0ad633bed1561c7455804b807;p=mesa.git

r600g: Swizzle vertex data only once.

Vertex data swizzles are already done in the vertex shader. Doing them twice
breaks BGRA vertex arrays for example.
---

diff --git a/src/gallium/drivers/r600/eg_state_inlines.h b/src/gallium/drivers/r600/eg_state_inlines.h
index 94a208442b9..031182aa4e2 100644
--- a/src/gallium/drivers/r600/eg_state_inlines.h
+++ b/src/gallium/drivers/r600/eg_state_inlines.h
@@ -636,38 +636,4 @@ out_unknown:
 	return ~0;
 }
 
-static INLINE uint32_t r600_translate_vertex_data_swizzle(enum pipe_format format)
-{
-	const struct util_format_description *desc = util_format_description(format);
-	unsigned i;
-	uint32_t word3;
-
-	assert(format);
-
-	if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
-		fprintf(stderr, "r600: Bad format %s in %s:%d\n",
-				util_format_short_name(format), __FUNCTION__, __LINE__);
-		return 0;
-	}
-
-	word3 = 0;
-	for (i = 0; i < desc->nr_channels; i++) {
-		switch (i) {
-		case 0:
-			word3 |= S_03000C_DST_SEL_X(desc->swizzle[0]);
-			break;
-		case 1:
-			word3 |= S_03000C_DST_SEL_Y(desc->swizzle[1]);
-			break;
-		case 2:
-			word3 |= S_03000C_DST_SEL_Z(desc->swizzle[2]);
-			break;
-		case 3:
-			word3 |= S_03000C_DST_SEL_W(desc->swizzle[3]);
-			break;
-		}
-	}
-	return word3;
-}
-
 #endif
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 208959dbaac..1535b9af945 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1276,7 +1276,10 @@ void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
 
 		word2 = format | S_030008_STRIDE(vertex_buffer->stride);
 
-		word3 = r600_translate_vertex_data_swizzle(rctx->vertex_elements->hw_format[i]);
+		word3 = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
+			S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
+			S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
+			S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
 
 		r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
 		r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);