From: Jacob Lifshay Date: Tue, 7 Mar 2023 05:14:16 +0000 (-0800) Subject: edit notes X-Git-Tag: opf_rfc_ls001_v3~190 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d1d9648e799a98c16d39f6313a7c2286ac10aec;p=libreriscv.git edit notes --- diff --git a/openpower/sv/int_fp_mv_reduced_insn_count.mdwn b/openpower/sv/int_fp_mv_reduced_insn_count.mdwn index 2329f034a..8c4ccaa02 100644 --- a/openpower/sv/int_fp_mv_reduced_insn_count.mdwn +++ b/openpower/sv/int_fp_mv_reduced_insn_count.mdwn @@ -38,9 +38,10 @@ Notes: * `fmvis` and `fishmv` have already been submitted to the ISA WG, so don't modify them! * PowerISA uses `s` and `.` suffixes instead of an immediate for Single and Rc=1 modes respectively. * PowerISA uses `w`, `uw`, `d`, and `ud` suffixes instead of an immediate for selecting between unsigned/signed 32-bit/64-bit. -* About the only operations we can realistically remove are Rc=1 versions, however Jacob thinks that isn't necessary. +* Jacob: About the only operations I can see that we can realistically remove are Rc=1 versions, however imho that isn't necessary. * Realistically we can't remove any of the Rc=0 instructions because it would make the instruction set non-orthogonal and it would penalize the code using those operations, almost all of which are quite common. -* Attempting to condense them into 6 instructions by undoing the PowerISA naming scheme works, but all that changed is the assembler mnemonics (in a bad way by being inconsistent with PowerISA), the instruction encodings don't change at all, unless we want to use an expanded opcode. +* Attempting to condense them into 6 instructions by undoing the PowerISA naming scheme works, but all that changed is the assembler mnemonics (in a bad way by being inconsistent with how PowerISA names things), the instruction encodings don't change at all, unless we want to use an expanded opcode. +* Jacob: I think we will want to keep the Single versions of moves/conversions from FPRs to GPRs, since it seems likely to run faster than the Double versions on some CPUs. # Rest of document not yet modified: