From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 29 Jul 2018 09:45:06 +0000 (+0100)
Subject: add tx clockhack
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d3896ef3fc39cd6ff193149cc28820f00a0e937;p=pinmux.git

add tx clockhack
---

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index f6d11f1..2d9f9dc 100644
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -232,6 +232,12 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
             typ = p['type']
             pname = p['name']
             n = name  
+            if typ == 'out' or typ == 'inout':
+                if not n.startswith('gpio'):  # XXX EURGH! horrible hack
+                    n_ = "{0}{1}".format(n, count)
+                else:
+                    n_ = n
+                ret.append(template.format("Bit#(1)", n_, ck, spc))
             if typ == 'in' or typ == 'inout':
                 #fname = self.pinname_in(pname)
                 n_ = "{0}{1}".format(n, count)