From: Gabe Black Date: Sun, 21 Jun 2009 16:43:55 +0000 (-0700) Subject: ARM: Clear out some inherited hangers on in util.isa and utility.hh. X-Git-Tag: Calvin_Submission~271 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d4ef8a398343800819930df97fcd79f7a9ba099;p=gem5.git ARM: Clear out some inherited hangers on in util.isa and utility.hh. --- diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index d56373225..dbd12e240 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -38,7 +38,6 @@ if env['TARGET_ISA'] == 'arm': Source('pagetable.cc') Source('regfile/regfile.cc') Source('tlb.cc') - Source('utility.cc') Source('vtophys.cc') SimObject('ArmTLB.py') diff --git a/src/arch/arm/isa/formats/util.isa b/src/arch/arm/isa/formats/util.isa index f60988bbb..5caab642c 100644 --- a/src/arch/arm/isa/formats/util.isa +++ b/src/arch/arm/isa/formats/util.isa @@ -192,30 +192,4 @@ output decoder {{ }}; -output exec {{ - - using namespace ArmISA; - - /// CLEAR ALL CPU INST/EXE HAZARDS - inline void - clear_exe_inst_hazards() - { - //CODE HERE - } - -#if FULL_SYSTEM - inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) - { - return NoFault; - } -#else - inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) - { - return NoFault; - } -#endif - - -}}; - diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc deleted file mode 100644 index 83d741297..000000000 --- a/src/arch/arm/utility.cc +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (c) 2003-2006 The Regents of The University of Michigan - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - * Stephen Hines - */ - -#include "arch/arm/regfile.hh" -#include "arch/arm/utility.hh" -#include "base/misc.hh" -#include "base/bitfield.hh" - -using namespace ArmISA; - -uint64_t -ArmISA::fpConvert(ConvertType cvt_type, double fp_val) -{ - - switch (cvt_type) - { - case SINGLE_TO_DOUBLE: - { - double sdouble_val = fp_val; - void *sdouble_ptr = &sdouble_val; - uint64_t sdp_bits = *(uint64_t *) sdouble_ptr; - return sdp_bits; - } - - case SINGLE_TO_WORD: - { - int32_t sword_val = (int32_t) fp_val; - void *sword_ptr = &sword_val; - uint64_t sword_bits= *(uint32_t *) sword_ptr; - return sword_bits; - } - - case WORD_TO_SINGLE: - { - float wfloat_val = fp_val; - void *wfloat_ptr = &wfloat_val; - uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr; - return wfloat_bits; - } - - case WORD_TO_DOUBLE: - { - double wdouble_val = fp_val; - void *wdouble_ptr = &wdouble_val; - uint64_t wdp_bits = *(uint64_t *) wdouble_ptr; - return wdp_bits; - } - - default: - panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type); - return 0; - } -} - -double -ArmISA::roundFP(double val, int digits) -{ - double digit_offset = pow(10.0,digits); - val = val * digit_offset; - val = val + 0.5; - val = floor(val); - val = val / digit_offset; - return val; -} - -double -ArmISA::truncFP(double val) -{ - int trunc_val = (int) val; - return (double) trunc_val; -} - -bool -ArmISA::getCondCode(uint32_t fcsr, int cc_idx) -{ - int shift = (cc_idx == 0) ? 23 : cc_idx + 24; - bool cc_val = (fcsr >> shift) & 0x00000001; - return cc_val; -} - -uint32_t -ArmISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val) -{ - int cc_idx = (cc_num == 0) ? 23 : cc_num + 24; - - fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) | - cc_val << cc_idx | - bits(fcsr, cc_idx - 1, 0); - - return fcsr; -} - -uint32_t -ArmISA::genInvalidVector(uint32_t fcsr_bits) -{ - //Set FCSR invalid in "flag" field - int invalid_offset = Invalid + Flag_Field; - fcsr_bits = fcsr_bits | (1 << invalid_offset); - - //Set FCSR invalid in "cause" flag - int cause_offset = Invalid + Cause_Field; - fcsr_bits = fcsr_bits | (1 << cause_offset); - - return fcsr_bits; -} - -bool -ArmISA::isNan(void *val_ptr, int size) -{ - switch (size) - { - case 32: - { - uint32_t val_bits = *(uint32_t *) val_ptr; - return (bits(val_bits, 30, 23) == 0xFF); - } - - case 64: - { - uint64_t val_bits = *(uint64_t *) val_ptr; - return (bits(val_bits, 62, 52) == 0x7FF); - } - - default: - panic("Type unsupported. Size mismatch\n"); - } -} - - -bool -ArmISA::isQnan(void *val_ptr, int size) -{ - switch (size) - { - case 32: - { - uint32_t val_bits = *(uint32_t *) val_ptr; - return (bits(val_bits, 30, 22) == 0x1FE); - } - - case 64: - { - uint64_t val_bits = *(uint64_t *) val_ptr; - return (bits(val_bits, 62, 51) == 0xFFE); - } - - default: - panic("Type unsupported. Size mismatch\n"); - } -} - -bool -ArmISA::isSnan(void *val_ptr, int size) -{ - switch (size) - { - case 32: - { - uint32_t val_bits = *(uint32_t *) val_ptr; - return (bits(val_bits, 30, 22) == 0x1FF); - } - - case 64: - { - uint64_t val_bits = *(uint64_t *) val_ptr; - return (bits(val_bits, 62, 51) == 0xFFF); - } - - default: - panic("Type unsupported. Size mismatch\n"); - } -} diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index a31fcd841..163cc6e33 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -35,13 +35,9 @@ #include "arch/arm/miscregs.hh" #include "arch/arm/types.hh" -#include "base/misc.hh" #include "base/types.hh" -#include "config/full_system.hh" #include "cpu/thread_context.hh" -class ThreadContext; - namespace ArmISA { inline bool @@ -70,19 +66,6 @@ namespace ArmISA { } } - //Floating Point Utility Functions - uint64_t fpConvert(ConvertType cvt_type, double fp_val); - double roundFP(double val, int digits); - double truncFP(double val); - - bool getCondCode(uint32_t fcsr, int cc); - uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); - uint32_t genInvalidVector(uint32_t fcsr); - - bool isNan(void *val_ptr, int size); - bool isQnan(void *val_ptr, int size); - bool isSnan(void *val_ptr, int size); - /** * Function to insure ISA semantics about 0 registers. * @param tc The thread context. @@ -113,6 +96,13 @@ namespace ArmISA { { tc->activate(0); } + + template + Fault + checkFpEnableFault(XC *xc) + { + return NoFault; + } };