From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 28 Oct 2022 00:01:45 +0000 (-0700)
Subject: fix bigint shift tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d58514beb36c313ccf13a0f14686bd68738f40d;p=openpower-isa.git

fix bigint shift tests
---

diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index 24608e47..86b287ad 100644
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -44,9 +44,9 @@ class BigIntCases(TestAccumulatorBase):
                 e = ExpectedState(pc=4, int_regs=gprs)
                 v = gprs[4]
                 v <<= sh % 64
-                mask = (1<<(sh%64))-1
+                mask = (1 << (sh % 64))-1
                 v |= gprs[6] & mask
-                e.intregs[3] = v         % 2 ** 64
+                e.intregs[3] = v % 2 ** 64
                 e.intregs[6] = (v >> 64) % 2 ** 64
                 self.add_case(prog, gprs, expected=e)
 
@@ -61,11 +61,11 @@ class BigIntCases(TestAccumulatorBase):
                 e = ExpectedState(pc=4, int_regs=gprs)
                 v = (gprs[4] << 64)
                 v >>= sh % 64
-                mask = ~((2 ** 64 - 1) >> (sh%64))
-                v |= (gprs[6] & mask)
-                print ("case_dsrd0", hex(mask), sh, hex(v))
-                e.intregs[3] = v         % 2 ** 64
-                e.intregs[6] = (v >> 64) % 2 ** 64
+                mask = ~((2 ** 64 - 1) >> (sh % 64))
+                v |= (gprs[6] & mask) << 64
+                print("case_dsrd0", hex(mask), sh, hex(v))
+                e.intregs[3] = (v >> 64) % 2 ** 64
+                e.intregs[6] = v % 2 ** 64
                 self.add_case(prog, gprs, expected=e)
 
 
@@ -98,27 +98,27 @@ class SVP64BigIntCases(TestAccumulatorBase):
     def case_sv_bigint_shift_right_by_scalar(self):
         """performs a bigint shift-right by scalar.
 
-        r0 starts off (as the carry-in) at 0x9000_0000_0000_0000
+        r5 starts off (as the carry-in) at 0x9000_0000_0000_0000
 
-        r18                   r17                   r16                      r4
+        r18                   r17                   r16                      r3
         0x0000_0000_5000_0002 0x8000_8000_8000_8001 0xffff_ffff_ffff_ffff >> 4
         0x0000_0000_0500_0000 0x2800_0800_0800_0800 0x1fff_ffff_ffff_ffff
 
         with the 4-bit part that drops out of the 4 LSBs of r16 ending up
         in r0
         """
-        prog = Program(list(SVP64Asm(["sv.dsrd/mrr *16,*16,4,0"])), False)
+        prog = Program(list(SVP64Asm(["sv.dsrd/mrr *16,*16,3,5"])), False)
         gprs = [0] * 32
-        gprs[0]  = 0x9000_0000_0000_0000
+        gprs[5] = 0x9000_0000_0000_0000
         gprs[16] = 0xffff_ffff_ffff_ffff
         gprs[17] = 0x8000_8000_8000_8001
         gprs[18] = 0x0000_0000_5000_0002
-        gprs[4] = 4
+        gprs[3] = 4
         svstate = SVP64State()
         svstate.vl = 3
         svstate.maxvl = 3
         e = ExpectedState(pc=8, int_regs=gprs)
-        e.intregs[0] = 0xf000_0000_0000_0000   # remainder (shifted out of 16)
+        e.intregs[5] = 0xf000_0000_0000_0000   # remainder (shifted out of 16)
         e.intregs[16] = 0x1fff_ffff_ffff_ffff
         e.intregs[17] = 0x2800_0800_0800_0800
         e.intregs[18] = 0x9000_0000_0500_0000  # initial r0 into top
@@ -130,27 +130,27 @@ class SVP64BigIntCases(TestAccumulatorBase):
         because the result is moved down by one register there is no need
         for reverse-gear.
 
-        r14 starts off as the carry-in: 0xa000_0000_0000_0000
+        r5 starts off as the carry-in: 0x0000_0000_0000_000a
 
-        r18                   r17                   r16                      r4
+        r18                   r17                   r16                      r3
         0x9000_0000_0001_0002 0x3fff_ffff_ffff_ffff 0x4000_0000_0000_0001 << 4
         r18                   r17                   r16
         0x0000_0000_0010_0023 0xffff_ffff_ffff_fff4 0x0000_0000_0000_0010
 
         with the top 4 bits of r18 being pushed into the LSBs of r14
         """
-        prog = Program(list(SVP64Asm(["sv.dsld *16,*16,4,14"])), False)
+        prog = Program(list(SVP64Asm(["sv.dsld *16,*16,3,5"])), False)
         gprs = [0] * 32
-        gprs[14] = 0x0000_0000_0000_000a
+        gprs[5] = 0x0000_0000_0000_000a
         gprs[16] = 0x4000_0000_0000_0001
         gprs[17] = 0x3fff_ffff_ffff_ffff
         gprs[18] = 0x9000_0000_0001_0002
-        gprs[4] = 4
+        gprs[3] = 4
         svstate = SVP64State()
         svstate.vl = 3
         svstate.maxvl = 3
         e = ExpectedState(pc=8, int_regs=gprs)
-        e.intregs[14] = 9
+        e.intregs[5] = 9
         e.intregs[16] = 0x0000_0000_0000_001a
         e.intregs[17] = 0xffff_ffff_ffff_fff4
         e.intregs[18] = 0x0000_0000_0010_0023