From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 23:52:04 +0000 (+0100)
Subject: whoops, regfiles are uppercase
X-Git-Tag: div_pipeline~620
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d685339284e5982980c52a3e14edd73cc51c425;p=soc.git

whoops, regfiles are uppercase
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 702e3b47..c6e41617 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -90,7 +90,7 @@ class NonProductionCore(Elaboratable):
                 (rdflag, read, wid, fuspec) = fspec
 
                 # "munge" the regfile port index, due to full-port access
-                if regfile in ['xer', 'cr']:
+                if regfile in ['XER', 'CA']:
                     if regname.startswith('full'):
                         rpidx = 0 # by convention, first port
                     else: