From: lkcl <lkcl@web>
Date: Fri, 12 Aug 2022 11:52:38 +0000 (+0100)
Subject: clarify about cache-inhibited LD/ST
X-Git-Tag: opf_rfc_ls005_v1~883
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d69e28724a4b2d8f0b4be2b3ccc577aa9de91cd;p=libreriscv.git

clarify about cache-inhibited LD/ST
---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 919bc5714..4076d15e1 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -102,7 +102,8 @@ in reading from the exact same memory location.
 For `LD-VSPLAT`, on non-cache-inhibited Loads, the read can occur
 just the once and be copied, rather than hitting the Data Cache
 multiple times with the same memory read at the same location.
-This would allow for memory-mapped peripherals to have multiple
+The benefit of Cache-inhibited LD-splats is that it allows
+for memory-mapped peripherals to have multiple
 data values read in quick succession and stored in sequentially
 numbered registers.
 
@@ -115,7 +116,9 @@ leaving just the last one as the "winner".  Bear in mind that predicate
 masks will skip some elements (in source non-zeroing mode).
 Cache-inhibited ST operations on the other hand **MUST** write out
 a Vector source multiple successive times to the exact same Scalar
-destination.
+destination. Just like Cache-inhibited LDs, multiple values may be
+written out in quick succession to a memory-mapped peripheral from
+sequentially-numbered registers.
 
 Note that there are no immediate versions of cache-inhibited LD/ST.