From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 8 Dec 2014 14:08:02 +0000 (+0100)
Subject: Added bool constructors to SigBit and SigSpec
X-Git-Tag: yosys-0.5~259
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d6e586df8128d4265499ef3f61c1a85ff3cc02a;p=yosys.git

Added bool constructors to SigBit and SigSpec
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 2f2f7c704..f5dbafe16 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2188,6 +2188,16 @@ RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
 	check();
 }
 
+RTLIL::SigSpec::SigSpec(bool bit)
+{
+	cover("kernel.rtlil.sigspec.init.bool");
+
+	width_ = 0;
+	hash_ = 0;
+	append_bit(bit);
+	check();
+}
+
 void RTLIL::SigSpec::pack() const
 {
 	RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index a488d3a6b..0157f3b7c 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -899,6 +899,7 @@ struct RTLIL::SigBit
 
 	SigBit() : wire(NULL), data(RTLIL::State::S0) { }
 	SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
+	SigBit(bool bit) : wire(NULL), data(bit ? RTLIL::S1 : RTLIL::S0) { }
 	SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
 	SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
 	SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
@@ -982,6 +983,7 @@ public:
 	SigSpec(std::vector<RTLIL::SigChunk> chunks);
 	SigSpec(std::vector<RTLIL::SigBit> bits);
 	SigSpec(std::set<RTLIL::SigBit> bits);
+	SigSpec(bool bit);
 
 	SigSpec(RTLIL::SigSpec &&other) {
 		width_ = other.width_;