From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 23 May 2020 14:57:25 +0000 (+0100)
Subject: add link to regspecs on wiki
X-Git-Tag: div_pipeline~913
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d738024bba9b86f4e96c36964c49a96170c2f41;p=soc.git

add link to regspecs on wiki
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index c39d863f..b25749c8 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -67,7 +67,7 @@ def go_record(n, name):
     r.rel.reset_less = True
     return r
 
-
+# see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
 def get_regspec_bitwidth(regspec, srcdest, idx):
     bitspec = regspec[srcdest][idx]
     wid = 0
@@ -96,6 +96,8 @@ class CompUnitRecord(RecordObject):
 
     :subkls:      the class (not an instance) needed to construct the opcode
     :rwid:        either an integer (specifies width of all regs) or a "regspec"
+
+    see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
     """
     def __init__(self, subkls, rwid, n_src=None, n_dst=None, name=None):
         RecordObject.__init__(self, name)
diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 599d2002..0eae72f0 100644
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -1,3 +1,7 @@
+"""
+Links:
+* https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
+"""
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec