From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 8 Feb 2022 12:18:54 +0000 (+0000)
Subject: loader working with arty a7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d772615665d66a2c281ccbb3fda0e02c169ef12;p=libresoc-litex.git

loader working with arty a7
---

diff --git a/versa_ecp5.py b/versa_ecp5.py
index 4b6b128..a3772e7 100755
--- a/versa_ecp5.py
+++ b/versa_ecp5.py
@@ -17,7 +17,7 @@ from litex.soc.integration.builder import (Builder, builder_args,
                                            builder_argdict)
 
 from libresoc import LibreSoC
-#from microwatt import Microwatt
+from microwatt import Microwatt
 
 # HACK!
 from litex.soc.integration.soc import SoCCSRHandler
@@ -126,9 +126,9 @@ class ArtyTestSoC(arty.BaseSoC):
         arty.BaseSoC.__init__(self,
             sys_clk_freq = sys_clk_freq,
             cpu_type     = "external",
-            cpu_cls      = LibreSoC,
-            cpu_variant  = "standardjtag",
-            #cpu_cls      = Microwatt,
+            #cpu_cls      = LibreSoC,
+            #cpu_variant  = "standardjtag",
+            cpu_cls      = Microwatt,
             variant      = "a7-100",
             toolchain    = "symbiflow",
             **kwargs)
@@ -151,10 +151,11 @@ def main():
 
     builder_args(parser)
     soc_sdram_args(parser)
+    trellis_args(parser)
     args = parser.parse_args()
 
+    loadext = ".svf"
     if args.fpga == "versa_ecp5":
-        trellis_args(parser)
         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                                **soc_sdram_argdict(args))
 
@@ -166,6 +167,7 @@ def main():
     elif args.fpga == "artya7100t":
         soc = ArtyTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                               **soc_sdram_argdict(args))
+        loadext = ".bit"
 
     else:
         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
@@ -180,10 +182,11 @@ def main():
         if args.load:
             prog = soc.platform.create_programmer()
             prog.load_bitstream(os.path.join(builder.gateware_dir,
-                                           soc.build_name + ".svf"))
+                                           soc.build_name + loadext))
     else:
         if args.load or args.build:
-            print("--load-from is incompatible with --load and --build", file=sys.stderr)
+            print("--load-from is incompatible with --load and --build",
+                  file=sys.stderr)
             sys.exit(1)
         prog = soc.platform.create_programmer()
         prog.load_bitstream(args.load_from)