From: Luke Kenneth Casson Leighton Date: Mon, 25 Jan 2021 14:10:55 +0000 (+0000) Subject: update 22nm page X-Git-Tag: convert-csv-opcode-to-binary~329 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d83516668ce48e39854b0dc4eed4a599f894c67;p=libreriscv.git update 22nm page --- diff --git a/22nm_PowerPI.mdwn b/22nm_PowerPI.mdwn index f34de3a55..3737777d1 100644 --- a/22nm_PowerPI.mdwn +++ b/22nm_PowerPI.mdwn @@ -20,6 +20,14 @@ broader appeal yet amortises the NREs across all of them. This is industry-standard practice: ST Micro and ATMEL use the exact same die in up to 12-14 different products. +Three different pin packages: + +* 400-450 pin FBGA 18mm 0.8mm and 14mm 0.6mm pitch, + single 32-bit DDR3/4 interface. Suitable for smaller products: + 0.8mm pitch is easier for low-cost China PCB manufacturing. +* 600-650 pin FPGA appx 20mm 0.6mm pitch, dual 32-bit DDR3/4 interfaces. + Suitable for 4k HD resolution screens and Graphics Card capability. + **Timeframe from when funding is received:** * 6-8 months for PHY negotiation and supply by IP Vendors (DDR4 is always