From: Tobias Platen <tplaten@posteo.de>
Date: Sat, 29 May 2021 18:46:18 +0000 (+0200)
Subject: test_ldst_pi.py: first version of test_dcache_random()
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d8792ef1f252383c48377152b33eeb7d1c47f75;p=soc.git

test_ldst_pi.py: first version of test_dcache_random()
---

diff --git a/src/soc/experiment/test/test_ldst_pi.py b/src/soc/experiment/test/test_ldst_pi.py
index b59efb5f..b2a7dcf1 100644
--- a/src/soc/experiment/test/test_ldst_pi.py
+++ b/src/soc/experiment/test/test_ldst_pi.py
@@ -320,20 +320,24 @@ def ldst_sim_dcache_random(dut):
     yield mmu.rin.prtbl.eq(0x1000000) # set process table
     yield
 
-    memsize = 256
+    memsize = 64
 
     for i in range(1024):
         addr = randint(0, memsize-1)
         data = randint(0, (1<<64)-1)
         addr *= 8
+        addr += 0x10000
 
         yield from pi_st(pi, addr, data, 8, msr_pr=1)
         yield
 
         ld_data = yield from pi_ld(pi, addr, 8, msr_pr=1)
 
-        print ("dcache_random random ld data", hex(data), hex(read))
         print ("addr",addr)
+        print ("dcache_random random ld data", hex(data), hex(ld_data))
+        if data!=ld_data:
+            print("==== data read at random test differs")
+        #assert(data==ld_data)
 
     yield
     stop = True
@@ -419,6 +423,22 @@ def test_dcache_random():
 
     # dcache_load at addr 0
     mem = {
+           0x10000:    # PARTITION_TABLE_2
+                       # PATB_GR=1 PRTB=0x1000 PRTS=0xb
+           b(0x800000000100000b),
+
+           0x30000:     # RADIX_ROOT_PTE
+                        # V = 1 L = 0 NLB = 0x400 NLS = 9
+           b(0x8000000000040009),
+
+           0x40000:     # RADIX_SECOND_LEVEL
+                        # V = 1 L = 1 SW = 0 RPN = 0
+                        # R = 1 C = 1 ATT = 0 EAA 0x7
+           b(0xc000000000000183),
+
+           0x1000000:   # PROCESS_TABLE_3
+                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
+           b(0x40000000000300ad),
     }
 
     # nmigen Simulation
@@ -436,5 +456,5 @@ if __name__ == '__main__':
     test_radixmiss_mmu()
     ### tests taken from src/soc/experiment/test/test_dcache.py
     test_dcache_regression()
-    #test_dcache_random()
+    test_dcache_random() #first access to memory fails - investigate
     #TODO test_dcache()