From: lkcl Date: Tue, 27 Oct 2020 01:44:33 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1918 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d8df2f921b1f185e164c50977a1ca54045ca95b;p=libreriscv.git --- diff --git a/openpower/sv/predication.mdwn b/openpower/sv/predication.mdwn index 4e29b45c9..5d7a989ba 100644 --- a/openpower/sv/predication.mdwn +++ b/openpower/sv/predication.mdwn @@ -42,7 +42,7 @@ As well-known weaknesses that compromise performance, very little use of OE=1 is (see [[masked_vector_chaining]]) -One of the design principles of SV is that the use of VL should be as closrly equivalent to a direct substitution of the scalar operations of the hardware for-loop as possible, as if those looped operations were actually in the instruction stream (as scalar operations) rather than being issued from the Vector loop. +One of the design principles of SV is that the use of VL should be as closely equivalent to a direct substitution of the scalar operations of the hardware for-loop as possible, as if those looped operations were actually in the instruction stream (as scalar operations) rather than being issued from the Vector loop. The implications here are that *register dependency hazards still have to be respected inter-element* even when (conceptually) pushed into the instruction stream from a hardware for-loop.