From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 Mar 2021 12:19:06 +0000 (+0000)
Subject: add in SVP64 RM Mode decoder
X-Git-Tag: convert-csv-opcode-to-binary~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d8e629e73912ca5f8c5f352db241f7f09ac47c1;p=soc.git

add in SVP64 RM Mode decoder
---

diff --git a/libreriscv b/libreriscv
index 923961d3..f6b82bb1 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 923961d3c598d9eeeaae184e50a448404f4b1d8f
+Subproject commit f6b82bb13e5c10c7924b3f0a911fb893fbbaf399
diff --git a/pinmux b/pinmux
index dcf51072..6ea0beaa 160000
--- a/pinmux
+++ b/pinmux
@@ -1 +1 @@
-Subproject commit dcf510721ff26108ec1f28f36cf59bbef3e2d37f
+Subproject commit 6ea0beaabfa993fc6cb369ab1c5731d8f6a839c3
diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 13c0215d..71617bfd 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -20,6 +20,7 @@ from soc.experiment.mem_types import LDSTException
 
 from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder
 from soc.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
+from soc.decoder.power_svp64_rm import SVP64RMModeDecode
 from soc.decoder.power_regspec_map import regspec_decode_read
 from soc.decoder.power_regspec_map import regspec_decode_write
 from soc.decoder.power_decoder import create_pdecode
@@ -925,6 +926,7 @@ class PowerDecode2(PowerDecodeSubset):
             self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector
             self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector
             self.loop_continue = Signal(1, name="loop_continue")
+            self.rm_dec = SVP64RMModeDecode("svp64_rm_dec")
         else:
             self.no_in_vec = Const(1, 1)
             self.no_out_vec = Const(1, 1)
@@ -989,6 +991,9 @@ class PowerDecode2(PowerDecodeSubset):
             # debug access to crout_svdec (used in get_pdecode_cr_out)
             self.crout_svdec = crout_svdec
 
+            # and SVP64 RM mode decoder
+            m.submodules.sv_rm_dec = self.rm_dec
+
         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
         reg = Signal(5, reset_less=True)
 
diff --git a/src/soc/decoder/power_svp64_rm.py b/src/soc/decoder/power_svp64_rm.py
index 93d9be57..dc5b71d1 100644
--- a/src/soc/decoder/power_svp64_rm.py
+++ b/src/soc/decoder/power_svp64_rm.py
@@ -102,22 +102,24 @@ class SVP64RMModeDecode(Elaboratable):
             with m.Case(3):
                 comb += self.mode.eq(SVP64RMMode.PREDRES) # predicate result
 
-        # identify predicate mode
-        with m.If(self.rm_in.mmode == 1):
-            comb += self.predmode.eq(SVP64PredMode.CR) # CR Predicate
-        with m.Elif(self.srcpred == 0):
-            comb += self.predmode.eq(SVP64PredMode.ALWAYS) # No predicate
-        with m.Else():
-            comb += self.predmode.eq(SVP64PredMode.INT) # non-zero src: INT
-
         # extract src/dest predicate.  use EXTRA3.MASK because EXTRA2.MASK
         # is in exactly the same bits
         srcmask = sel(m, self.rm_in.extra, EXTRA3.MASK)
         dstmask = self.rm_in.mask
         with m.If(self.ptype_in == SVPtype.P2):
             comb += self.srcpred.eq(srcmask)
+        with m.Else():
+            comb += self.srcpred.eq(dstmask)
         comb += self.dstpred.eq(dstmask)
 
+        # identify predicate mode
+        with m.If(self.rm_in.mmode == 1):
+            comb += self.predmode.eq(SVP64PredMode.CR) # CR Predicate
+        with m.Elif(self.srcpred == 0):
+            comb += self.predmode.eq(SVP64PredMode.ALWAYS) # No predicate
+        with m.Else():
+            comb += self.predmode.eq(SVP64PredMode.INT) # non-zero src: INT
+
         # TODO: detect zeroing mode, saturation mode, a few more.
 
         return m