From: Luke Kenneth Casson Leighton Date: Sat, 6 Jun 2020 18:46:41 +0000 (+0100) Subject: work out how to initialise memory directly X-Git-Tag: div_pipeline~523 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d91dc5b1a91bb91dd884f9048fa8432049710eb;p=soc.git work out how to initialise memory directly --- diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 602a9984..5e6fe2e9 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -1,4 +1,4 @@ -from nmigen import Module, Signal +from nmigen import Module, Signal, ResetSignal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil @@ -151,8 +151,7 @@ class TestRunner(FHDLTestCase): mem = l0.mem.mem memlist = [] for i in range(mem.depth): - memlist.append(sim.mem.ld(i*8, 8)) - mem.init = memlist + yield mem._array[i].eq(sim.mem.ld(i*8, 8)) print (mem, mem.depth, mem.width) print ("mem init", list(map(hex,memlist)))