From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 10 Jan 2020 23:07:46 +0000 (-0800)
Subject: synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro
X-Git-Tag: working-ls180~870^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d94e18100a6fe61805e94e754b199826571e7ef;p=yosys.git

synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 51d2cbbd2..5867f5d1c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -26,13 +26,16 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
-                           // to one LUT6 (instead of a LUT5 + LUT2)
-
 struct SynthXilinxPass : public ScriptPass
 {
 	SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
 
+	void on_register() YS_OVERRIDE
+	{
+		RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate
+								    // to one LUT6 (instead of a LUT5 + LUT2)
+	}
+
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -555,7 +558,11 @@ struct SynthXilinxPass : public ScriptPass
 				run("techmap " + techmap_args);
 				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
 				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
-				abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
+				auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
+				if (active_design->scratchpad.count(k))
+					abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+				else
+					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
 				abc9_opts += " -nomfs";
 				if (nowidelut)
 					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";