From: Rob Clark <robdclark@chromium.org>
Date: Sat, 21 Mar 2020 16:49:27 +0000 (-0700)
Subject: freedreno/a6xx: register update
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d9a794f356beb73f08278df06fa1ef5670d012c;p=mesa.git

freedreno/a6xx: register update

No functional change, and this register isn't used in userspace.  Just
syncing from envytools tree to eliminate the delta.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
---

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 1fdc21e9839..967f1382401 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -1072,7 +1072,9 @@ to upconvert to 32b float internally?
 		<bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
 		<bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
 	</reg32>
-	<reg32 offset="0x0213" name="RBBM_STATUS3"/>
+	<reg32 offset="0x0213" name="RBBM_STATUS3">
+		<bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
+	</reg32>
 	<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
 	<reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
 	<reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>