From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 7 Nov 2023 04:37:07 +0000 (-0800)
Subject: support TRAP being called without setting a trap_bit
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7da851699654782e712b4b5bc7c7be9df2f451ca;p=openpower-isa.git

support TRAP being called without setting a trap_bit
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 7f547815..0c5199e2 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1372,7 +1372,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         if self.is_svp64_mode:
             self.spr['SVSRR0'] = self.namespace['SVSTATE'].value
         self.trap_nia = SelectableInt(trap_addr | (kaivb & ~0x1fff), 64)
-        self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1
+        if trap_bit is not None:
+            self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1
 
         # set exception bits.  TODO: this should, based on the address
         # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these