From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 15:22:26 +0000 (-0700)
Subject: Do not double count cells in abc
X-Git-Tag: working-ls180~1191^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7dc15bdd2dff8493ee5786845a5e39427bf3779d;p=yosys.git

Do not double count cells in abc
---

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 15e79f9d1..65c7d1bb8 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1172,8 +1172,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 					continue;
 				}
 			}
-
-			cell_stats[RTLIL::unescape_id(c->type)]++;
+			else
+				cell_stats[RTLIL::unescape_id(c->type)]++;
 
 			if (c->type == "\\_const0_" || c->type == "\\_const1_") {
 				RTLIL::SigSig conn;