From: lkcl <lkcl@web>
Date: Tue, 15 Dec 2020 03:02:40 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1318
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7dc9974f511e3bccf1741707caaa72780642bc23;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 30e56b8b3..56441bd37 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -99,15 +99,16 @@ where `r20`, `r25`, and `r30` are standard OpenPower register names.
 Those names correspond to `SVR20_00`, `SVR25_00`, and `SVR30_00`.
 
 pseudocode:
+
 ```C++
-const size_t STD_TO_SV_SHIFT = 2; // gets bigger as reg files expand to 256, 512, ... registers
+    const size_t STD_TO_SV_SHIFT = 2; // gets bigger as reg files expand to 256, 512, ... registers
 
-VL = 7; // setvli (omitting maxvl here)
+    VL = 7; // setvli (omitting maxvl here)
 
-for(size_t i = 0; i < VL; i++) {
-    regs[(20 << STD_TO_SV_SHIFT) + i] = regs[(25 << STD_TO_SV_SHIFT) + i]
-        + regs[(30 << STD_TO_SV_SHIFT) + i];
-}
+    for(size_t i = 0; i < VL; i++) {
+        regs[(20 << STD_TO_SV_SHIFT) + i] = regs[(25 << STD_TO_SV_SHIFT) + i]
+            + regs[(30 << STD_TO_SV_SHIFT) + i];
+    }
 ```
 
 Standard PowerISA Integer registers are aliased to some of the SV integer registers: