From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 00:29:45 +0000 (-0700)
Subject: Fix issue with part of PI being 1'bx
X-Git-Tag: working-ls180~1208^2~131
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7dca8def52fdd3a0e450d3f554c328904636798d;p=yosys.git

Fix issue with part of PI being 1'bx
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index b98b36319..1235af142 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -944,11 +944,13 @@ void AigerReader::post_process()
 			if (other_wire) {
 				other_wire->port_input = false;
 				other_wire->port_output = false;
-				if (wire->port_input)
-					module->connect(other_wire, SigSpec(wire, i));
-				else
-					module->connect(SigSpec(wire, i), other_wire);
 			}
+			if (wire->port_input && other_wire)
+				module->connect(other_wire, SigSpec(wire, i));
+			else
+								  // Since we skip POs that are connected to Sx,
+								  // re-connect them here
+				module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
 		}
 	}
 
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 0b83c34a3..64b625efe 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -262,3 +262,8 @@ endmodule
 module abc9_test025(input [3:0] i, output [3:0] o);
 abc9_test024_sub a(i[2:1], o[2:1]);
 endmodule
+
+module abc9_test026(output [3:0] o, p);
+assign o = { 1'b1, 1'bx };
+assign p = { 1'b1, 1'bx, 1'b0 };
+endmodule