From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 17 Jun 2019 19:58:41 +0000 (-0700)
Subject: Merge branch 'xaig' into xaig_dff
X-Git-Tag: working-ls180~881^2^2~297
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7dd3a7f161d57f8c1f4a26cc5645bbec1c9e687a;p=yosys.git

Merge branch 'xaig' into xaig_dff
---

7dd3a7f161d57f8c1f4a26cc5645bbec1c9e687a
diff --cc passes/techmap/abc9.cc
index e234ab28d,9c4e6bb39..40c75159d
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@@ -501,30 -498,8 +501,14 @@@ void abc9_module(RTLIL::Design *design
  				for (int i = 0; i < GetSize(wire); i++)
  					output_bits.insert({wire, i});
  			}
 +
 +			auto jt = w->attributes.find("\\init");
 +			if (jt != w->attributes.end()) {
 +				auto r = remap_wire->attributes.insert(std::make_pair("\\init", jt->second));
 +				log_assert(r.second);
 +			}
  		}
  
- 		dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes;
- 		for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
- 			RTLIL::Cell* cell = it->second;
- 			if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) {
- 				it = module->cells_.erase(it);
- 				continue;
- 			}
- 			RTLIL::Module* box_module = design->module(cell->type);
- 			if (box_module && box_module->attributes.count("\\abc_box_id")) {
- 				erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters)));
- 				it = module->cells_.erase(it);
- 				continue;
- 			}
- 			++it;
- 		}
- 		// Do the same for module connections
  		for (auto &it : module->connections_) {
  			auto &signal = it.first;
  			auto bits = signal.bits();