From: lkcl Date: Sun, 26 Jun 2022 13:04:33 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~1517 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7dd4adb3424bafd59755b6100a5407ee6b2f6e64;p=libreriscv.git --- diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 4fcacdb09..c80e3b866 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -74,10 +74,10 @@ Parallel Carry Lookahead. It can clearly be seen that the carry chains from one 64 bit add to the next, the end result being that a -256-bit "Big Integer Add" has been performed, and that -CA contains the 257th bit. A one-instruction 512-bit Add +256-bit "Big Integer Add with Carry" has been performed, and that +CA contains the 257th bit. A one-instruction 512-bit Add-with-Carry may be performed by setting VL=8, and a one-instruction -1024-bit add by setting VL=16, and so on. More on +1024-bit Add-with-Carry by setting VL=16, and so on. More on this in [[openpower/sv/biginteger]] # v3.0B/v3.1 relevant instructions