From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 19:43:56 +0000 (-0700)
Subject: Fix TODOs
X-Git-Tag: working-ls180~1003^2~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7de9c33931020068b285e262bbf239385fcb5c2d;p=yosys.git

Fix TODOs
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index bcf966a8a..6b6151564 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -103,11 +103,6 @@ code sigA sigB sigC sigD sigM clock
 	}
 	else
 		sigM = P;
-	// TODO: Check if necessary
-	// This sigM could have no users if downstream $add
-	//   is narrower than $mul result, for example
-	if (sigM.empty())
-		reject;
 
 	clock = port(dsp, \CLK, SigBit());
 endcode
@@ -159,16 +154,6 @@ match preAdd
 	optional
 endmatch
 
-code sigA sigD
-	// TODO: Check if this is necessary?
-	if (preAdd) {
-		sigA = port(preAdd, \A);
-		sigD = port(preAdd, \B);
-		if (GetSize(sigA) < GetSize(sigD))
-			std::swap(sigA, sigD);
-	}
-endcode
-
 // (4) If pre-adder was present, find match 'A' input for A2REG
 //     If pre-adder was not present, move ADREG to A2REG
 //     Then match 'A' input for A1REG
diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index 38a5a8d24..5697ee737 100644
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -79,11 +79,6 @@ endcode
 //     (attached to at most two $mux cells that implement clock-enable or
 //      reset functionality, using a subpattern discussed below)
 code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
-	// TODO: Any downside to allowing this?
-	// If this DSP implements an accumulator, do not attempt to match
-	if (sigC == sigP)
-		reject;
-
 	argQ = sigC;
 	subpattern(in_dffe);
 	if (dff) {