From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 17 May 2020 16:08:22 +0000 (+0100)
Subject: use Cat(*list) on CR mask
X-Git-Tag: div_pipeline~1112
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7df635d6d1e790b931b61951fa7a2322182d68c1;p=soc.git

use Cat(*list) on CR mask
---

diff --git a/src/soc/cr/main_stage.py b/src/soc/cr/main_stage.py
index b3b2b44f..e29d5eed 100644
--- a/src/soc/cr/main_stage.py
+++ b/src/soc/cr/main_stage.py
@@ -77,8 +77,7 @@ class CRMainStage(PipeModBase):
 
         # replicate every fxm field in the insn to 4-bit, as a mask
         mask = Signal(32, reset_less=True)
-        for i in range(8):
-            comb += mask[i*4:(i+1)*4].eq(Repl(fxm[i], 4))
+        comb += mask.eq(Cat(*[Repl(fxm[i], 4) for i in range(8)]))
 
         #################################
         ##### main switch statement #####
@@ -132,6 +131,7 @@ class CRMainStage(PipeModBase):
                 comb += cr_o.eq((self.i.a[0:32] & mask) |
                                      (self.i.cr & ~mask))
 
+            ##### mfcr #####
             with m.Case(InternalOp.OP_MFCR):
                 # mfocrf
                 with m.If(move_one):