From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 8 May 2019 10:39:10 +0000 (+0100)
Subject: rename variable wid -> dep
X-Git-Tag: div_pipeline~2104
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7df8f1a16741a6f9bc42a7a39aa33ecb6e6fd957;p=soc.git

rename variable wid -> dep
---

diff --git a/src/scoreboard/global_pending.py b/src/scoreboard/global_pending.py
index f8ab4015..e3bcb555 100644
--- a/src/scoreboard/global_pending.py
+++ b/src/scoreboard/global_pending.py
@@ -33,13 +33,13 @@ class GlobalPending(Elaboratable):
         for v in fu_vecs:
             assert len(v) == dep, "FU Vector must be same width as regfile"
 
-        self.g_pend_o = Signal(wid, reset_less=True)  # global pending vector
+        self.g_pend_o = Signal(dep, reset_less=True)  # global pending vector
 
     def elaborate(self, platform):
         m = Module()
 
         pend_l = []
-        for i in range(self.reg_width): # per-register
+        for i in range(self.reg_dep): # per-register
             vec_bit_l = []
             for v in self.fu_vecs:
                 vec_bit_l.append(v[i])             # fu bit for same register