From: lkcl <lkcl@web>
Date: Tue, 25 Apr 2023 16:43:12 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e2583d749d919fff36e5ff34335bf1b1d9fbe38;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 6d09990b9..865066dae 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -1,7 +1,5 @@
 # New instructions for CR/INT predication
 
-**DRAFT STATUS**
-
 See:
 
 * main bugreport for crweirds
@@ -11,14 +9,6 @@ See:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=558#c47>
 * [[discussion]]
 
-# Bit ordering.
-
-Please see [[svp64/appendix]] regarding CR bit ordering and for
-the definition of `CR{n}`
-
-# Instructions
-
-
 ## crrweird
 
 CW2-Form