From: Tim Newsome <tim@sifive.com>
Date: Fri, 16 Dec 2016 05:12:34 +0000 (-0800)
Subject: Fix single stepping over faulting instructions. (#80)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e31f495358df52e49b9a5fec7ce273d706b1300;p=riscv-isa-sim.git

Fix single stepping over faulting instructions. (#80)
---

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 36e7896..eb9fe4b 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -190,6 +190,11 @@ miss:
     {
       take_trap(t, pc);
       n = instret;
+
+      if (unlikely(state.single_step == state.STEP_STEPPED)) {
+        state.single_step = state.STEP_NONE;
+        enter_debug_mode(DCSR_CAUSE_STEP);
+      }
     }
     catch (trigger_matched_t& t)
     {