From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 01:39:29 +0000 (+0100)
Subject: update submodule for ISA tables
X-Git-Tag: div_pipeline~637^2~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e32307f763f693a405a5d1691fb23894bcd3be3;p=soc.git

update submodule for ISA tables
---

diff --git a/libreriscv b/libreriscv
index 71d70e4c..1970241a 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 71d70e4c753d1171c1fb83e1b9f9d78c9372f8d1
+Subproject commit 1970241a6db97d4ace1e053e72f2a3d9462e98b2