From: Luke Kenneth Casson Leighton Date: Tue, 24 Apr 2018 12:46:05 +0000 (+0100) Subject: clarify X-Git-Tag: convert-csv-opcode-to-binary~5577 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e592431d713422d7a64a83a0ef6294a94e62c56;p=libreriscv.git clarify --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index c8235749e..b9f94b3fc 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -936,9 +936,9 @@ from actual (internal) parallel hardware. It's an API in effect that's designed to be slotted in to an existing implementation (just after instruction decode) with minimum disruption and effort. -* minus: the complexity of having to use register renames, OoO, VLIW, - register file cacheing, all of which has been done before but is a - pain +* minus: the complexity (if full parallelism is to be exploited) + of having to use register renames, OoO, VLIW, register file cacheing, + all of which has been done before but is a pain * plus: transparent re-use of existing opcodes as-is just indirectly saying "this register's now a vector" which * plus: means that future instructions also get to be inherently