From: Michael Nolan Date: Sat, 29 Feb 2020 22:45:02 +0000 (-0500) Subject: Add tests for minor_30 and minor_31 decoding tables X-Git-Tag: div_pipeline~1802 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e5ec65b6ffcd466fcb8aa192122aa7e1b48d758;p=soc.git Add tests for minor_30 and minor_31 decoding tables --- diff --git a/src/decoder/power_decoder.py b/src/decoder/power_decoder.py index 22e52435..52e4f791 100644 --- a/src/decoder/power_decoder.py +++ b/src/decoder/power_decoder.py @@ -30,6 +30,8 @@ class PowerDecoder(Elaboratable): with m.Switch(self.opcode_in): for row in self.opcodes: opcode = int(row['opcode'], 0) + if not row['unit']: + continue with m.Case(opcode): comb += self.function_unit.eq(Function[row['unit']]) comb += self.internal_op.eq(InternalOp[row['internal op']]) diff --git a/src/decoder/test/test_power_decoder.py b/src/decoder/test/test_power_decoder.py index 5f3f3e2e..df85c6e8 100644 --- a/src/decoder/test/test_power_decoder.py +++ b/src/decoder/test/test_power_decoder.py @@ -43,6 +43,8 @@ class DecoderTestCase(FHDLTestCase): def process(): for row in dut.opcodes: + if not row['unit']: + continue yield opcode.eq(int(row['opcode'], 0)) yield Delay(1e-6) signals = [(function_unit, Function, 'unit'), @@ -80,10 +82,19 @@ class DecoderTestCase(FHDLTestCase): def test_major(self): self.run_test(6, "major.csv") + self.generate_ilang(6, "major.csv") def test_minor_19(self): self.run_test(3, "minor_19.csv") + self.generate_ilang(3, "minor_19.csv") + def test_minor_30(self): + self.run_test(4, "minor_30.csv") + self.generate_ilang(4, "minor_30.csv") + + def test_minor_31(self): + self.run_test(10, "minor_31.csv") + self.generate_ilang(10, "minor_31.csv") if __name__ == "__main__": unittest.main()