From: Luke Kenneth Casson Leighton Date: Mon, 10 Jan 2022 23:03:25 +0000 (+0000) Subject: LoadStore1 priv_mode was not being correctly picked up by the MMU X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e62e7e703f666fe89eecb3ac163a26699bd1acf;p=soc.git LoadStore1 priv_mode was not being correctly picked up by the MMU priv_mode needs to come from the original LD/ST request (or the fetch), which was not happening --- diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index 36836c67..081ff019 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -119,8 +119,6 @@ class LoadStore1(PortInterfaceBase): #self.atomic_last = Signal() #self.rc = Signal() self.nc = Signal() # non-cacheable access - self.virt_mode = Signal() - self.priv_mode = Signal() self.mode_32bit = Signal() # XXX UNUSED AT PRESENT self.state = Signal(State) self.instr_fault = Signal() # indicator to request i-cache MMU lookup @@ -447,7 +445,7 @@ class LoadStore1(PortInterfaceBase): m.d.comb += m_out.valid.eq(mmureq) m.d.comb += m_out.iside.eq(self.instr_fault) m.d.comb += m_out.load.eq(ldst_r.load) - m.d.comb += m_out.priv.eq(self.priv_mode) + m.d.comb += m_out.priv.eq(ldst_r.priv_mode) # m_out.priv <= r.priv_mode; TODO m.d.comb += m_out.tlbie.eq(self.tlbie) # m_out.mtspr <= mmu_mtspr; # TODO diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index 24be3f54..c1d4d74f 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -225,7 +225,6 @@ class FSMMMUStage(ControlBase): # from accepting any other LD/ST requests. comb += valid.eq(1) # start "pulse" comb += ldst.instr_fault.eq(blip) - comb += ldst.priv_mode.eq(~msr_i[MSR.PR]) comb += ldst.maddr.eq(cia_i) # XXX should not access this! comb += done.eq(ldst.done)