From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 01:43:17 +0000 (-0700)
Subject: Trim shiftx_width when upper bits are 1'bx
X-Git-Tag: working-ls180~1085^2~72
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e7965ca7b3bbeb79cb70014da7bc48c08a74adb;p=yosys.git

Trim shiftx_width when upper bits are 1'bx
---

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index 3f4efebe9..d3ba0109f 100644
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -164,6 +164,11 @@ endmatch
 
 code shiftx_width
 	shiftx_width = param(shiftx, \A_WIDTH).as_int();
+	while (shiftx_width > 1) {
+		if (port(shiftx, \A)[shiftx_width-1] != State::Sx)
+			break;
+		--shiftx_width;
+	}
 endcode
 
 match first
@@ -177,7 +182,7 @@ code
 	chain.push_back(first);
 	subpattern(tail);
 finally
-	if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int())
+	if (GetSize(chain) == shiftx_width)
 		accept;
 	chain.clear();
 endcode