From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 13 May 2020 15:35:41 +0000 (-0400)
Subject: Update cmp test in test_caller.py
X-Git-Tag: div_pipeline~1262
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e7f0d13e8d8c4b77c62fef25089b1a76294df28;p=soc.git

Update cmp test in test_caller.py
---

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index f1224f48..a0381b9d 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -181,11 +181,11 @@ class DecoderTestCase(FHDLTestCase):
     def test_cmp(self):
         lst = ["addis 1, 0, 0xffff",
                "addis 2, 0, 0xffff",
-               "cmp cr0, 0, 1, 2",
+               "cmp cr2, 0, 1, 2",
                "mfcr 3"]
         with Program(lst) as program:
             sim = self.run_tst_program(program)
-            self.assertEqual(sim.gpr(3), SelectableInt(0x20000000, 64))
+            self.assertEqual(sim.gpr(3), SelectableInt(0x200000, 64))
 
     def test_slw(self):
         lst = ["slw 1, 3, 2"]