From: Lukasz Dalek Date: Mon, 18 May 2020 19:02:19 +0000 (+0200) Subject: Support logic typed parameters X-Git-Tag: working-ls180~398^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e83a51;p=yosys.git Support logic typed parameters Signed-off-by: Lukasz Dalek --- diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 656910c0c..dfdb11cf0 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1337,8 +1337,6 @@ param_signed: param_integer: TOK_INTEGER { - if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("Internal error in param_integer - should not happen?"); astbuf1->children.push_back(new AstNode(AST_RANGE)); astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true)); astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true)); @@ -1347,16 +1345,19 @@ param_integer: param_real: TOK_REAL { - if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real."); astbuf1->children.push_back(new AstNode(AST_REALVALUE)); } +param_logic: + TOK_LOGIC { + // SV LRM 6.11, Table 6-8: logic -- 4-state, user-defined vector size, unsigned + astbuf1->is_signed = false; + astbuf1->is_logic = true; + } + param_range: range { if ($1 != NULL) { - if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("integer/real parameters should not have a range."); astbuf1->children.push_back($1); } }; @@ -1365,8 +1366,10 @@ param_integer_type: param_integer param_signed param_range_type: type_vec param_signed param_range param_implicit_type: param_signed param_range +param_integer_vector_type: param_logic param_signed param_range + param_type: - param_integer_type | param_real | param_range_type | param_implicit_type | + param_integer_type | param_integer_vector_type | param_real | param_range_type | param_implicit_type | hierarchical_type_id { astbuf1->is_custom_type = true; astbuf1->children.push_back(new AstNode(AST_WIRETYPE));