From: lkcl <lkcl@web>
Date: Mon, 5 Sep 2022 00:31:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~696
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e8b47992399ac1c653d36ea6fd5d4c49ea8ea3d;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 726db6904..149a0201d 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -166,6 +166,34 @@ Core SVP64 instructions:
 Beyond this point are additional **Scalar** instructions related to
 specific workloads that have nothing to do with the SV Specification*
 
+# Guarantees in Simple-V
+
+Providing long-term stability in an ISA is extremely challenging.
+It requires certain guarantees to be provided.
+
+* Firstly: that instructions will never be ambiguously-defined.
+* Secondly, that no instruction shall change meaning to produce
+  different results on different hardware (present or future)
+* Thirdly, that implementors are not permitted to either add
+  arbitrary features nor implement features in an incompatible
+  way.
+* Fourthly, that any part of Simple-V not implemented by
+  a lower Compliancy Level is *required* to raise an illegal
+  instruction trap.
+
+In particular, given the strong recent emphasis and interest in
+"Scalable Vector" ISAs, it is most unfortunate that both ARM SVE
+and RISC-V RVV permit the exact same instruction to produce
+different results on different hardware depending on a
+"Silicon Partner" hardware choice. This choice catastrophically
+and irrevocably causes binary non-interoperability despite being
+a "feature".  Explained in <https://m.youtube.com/watch?v=HNEm8zmkjBU>
+
+It is therefore *guaranteed* that extensions to the register file
+width and quantity in Simple-V shall only be made in future by
+explicit means, ensuring binary compatibility.
+
+
 # Optional Scalar instructions
 
 **Additional Instructions for specific purposes (not SVP64)**