From: Robert Suchanek Date: Tue, 9 Apr 2019 09:30:26 +0000 (+0800) Subject: [MIPS] Add RDHWR with the SEL field for MIPS R6. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e96e219a4fc703282ea5b0cc8845a96c01ca030;p=binutils-gdb.git [MIPS] Add RDHWR with the SEL field for MIPS R6. In Release 6 of the MIPS architecture [1], instruction RDHWR supports a 3rd operand to serve as the 3-bit select field for the hardware register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 332-334 opcodes/ * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. gas/ * testsuite/gas/mips/mips.exp: Run hwr-names test. * testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with the SEL field. * testsuite/gas/mips/mipsr6@hwr-names.d: New file. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index dd53712c4f8..354aae195d7 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2019-04-09 Robert Suchanek + + * testsuite/gas/mips/mips.exp: Run hwr-names test. + * testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with + the SEL field. + * testsuite/gas/mips/mipsr6@hwr-names.d: New file. + 2019-04-08 H.J. Lu * config/tc-i386.c (output_insn): Support diff --git a/gas/testsuite/gas/mips/hwr-names.s b/gas/testsuite/gas/mips/hwr-names.s index f0e056b78fd..41e7b49dcb8 100644 --- a/gas/testsuite/gas/mips/hwr-names.s +++ b/gas/testsuite/gas/mips/hwr-names.s @@ -40,5 +40,16 @@ text_label: rdhwr $0, $30 rdhwr $0, $31 + .ifdef r6 + rdhwr $0, $4, 0 + rdhwr $0, $4, 1 + rdhwr $0, $4, 2 + rdhwr $0, $4, 3 + rdhwr $0, $4, 4 + rdhwr $0, $4, 5 + rdhwr $0, $4, 6 + rdhwr $0, $4, 7 + .endif + # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... .space 8 diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 31e155b3144..a009c6eae3d 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1342,6 +1342,8 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "hwr-names-numeric" run_dump_test "hwr-names-mips32r2" run_dump_test "hwr-names-mips64r2" + run_dump_test_arches "hwr-names" [mips_arch_list_matching mips32r6 \ + !micromipsr6] run_dump_test "ldstla-32" run_dump_test "ldstla-32-mips3" diff --git a/gas/testsuite/gas/mips/mipsr6@hwr-names.d b/gas/testsuite/gas/mips/mipsr6@hwr-names.d new file mode 100644 index 00000000000..e44a120c384 --- /dev/null +++ b/gas/testsuite/gas/mips/mipsr6@hwr-names.d @@ -0,0 +1,51 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32r6 -M gpr-names=numeric,hwr-names=mips32r6 +#name: MIPS HWR disassembly (mips32r6) +#as: -32 +#source: hwr-names.s + +# Check objdump's handling of -M hwr-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 7c00003b rdhwr \$0,hwr_cpunum +0+0004 <[^>]*> 7c00083b rdhwr \$0,hwr_synci_step +0+0008 <[^>]*> 7c00103b rdhwr \$0,hwr_cc +0+000c <[^>]*> 7c00183b rdhwr \$0,hwr_ccres +0+0010 <[^>]*> 7c00203b rdhwr \$0,\$4 +0+0014 <[^>]*> 7c00283b rdhwr \$0,\$5 +0+0018 <[^>]*> 7c00303b rdhwr \$0,\$6 +0+001c <[^>]*> 7c00383b rdhwr \$0,\$7 +0+0020 <[^>]*> 7c00403b rdhwr \$0,\$8 +0+0024 <[^>]*> 7c00483b rdhwr \$0,\$9 +0+0028 <[^>]*> 7c00503b rdhwr \$0,\$10 +0+002c <[^>]*> 7c00583b rdhwr \$0,\$11 +0+0030 <[^>]*> 7c00603b rdhwr \$0,\$12 +0+0034 <[^>]*> 7c00683b rdhwr \$0,\$13 +0+0038 <[^>]*> 7c00703b rdhwr \$0,\$14 +0+003c <[^>]*> 7c00783b rdhwr \$0,\$15 +0+0040 <[^>]*> 7c00803b rdhwr \$0,\$16 +0+0044 <[^>]*> 7c00883b rdhwr \$0,\$17 +0+0048 <[^>]*> 7c00903b rdhwr \$0,\$18 +0+004c <[^>]*> 7c00983b rdhwr \$0,\$19 +0+0050 <[^>]*> 7c00a03b rdhwr \$0,\$20 +0+0054 <[^>]*> 7c00a83b rdhwr \$0,\$21 +0+0058 <[^>]*> 7c00b03b rdhwr \$0,\$22 +0+005c <[^>]*> 7c00b83b rdhwr \$0,\$23 +0+0060 <[^>]*> 7c00c03b rdhwr \$0,\$24 +0+0064 <[^>]*> 7c00c83b rdhwr \$0,\$25 +0+0068 <[^>]*> 7c00d03b rdhwr \$0,\$26 +0+006c <[^>]*> 7c00d83b rdhwr \$0,\$27 +0+0070 <[^>]*> 7c00e03b rdhwr \$0,\$28 +0+0074 <[^>]*> 7c00e83b rdhwr \$0,\$29 +0+0078 <[^>]*> 7c00f03b rdhwr \$0,\$30 +0+007c <[^>]*> 7c00f83b rdhwr \$0,\$31 +0+0080 <[^>]*> 7c00203b rdhwr \$0,\$4 +0+0084 <[^>]*> 7c00207b rdhwr \$0,\$4,1 +0+0088 <[^>]*> 7c0020bb rdhwr \$0,\$4,2 +0+008c <[^>]*> 7c0020fb rdhwr \$0,\$4,3 +0+0090 <[^>]*> 7c00213b rdhwr \$0,\$4,4 +0+0094 <[^>]*> 7c00217b rdhwr \$0,\$4,5 +0+0098 <[^>]*> 7c0021bb rdhwr \$0,\$4,6 +0+009c <[^>]*> 7c0021fb rdhwr \$0,\$4,7 + \.\.\. diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 27557ebb080..b6d4de3ab7e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2019-04-09 Robert Suchanek + + * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. + 2019-04-08 H.J. Lu * i386-opc.tbl: Consolidate AVX512 BF16 entries. diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 837da6bd992..91f60275f31 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1781,6 +1781,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, I37 }, {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, I37 }, {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_1, 0, I33, 0, 0 }, +{"rdhwr", "t,K,+O", 0x7c00003b, 0xffe0063f, WR_1, 0, I37, 0, 0 }, {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_1, 0, I33, 0, 0 }, /* rfe is moved below as it now conflicts with tlbgp */ {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 },