From: Clifford Wolf Date: Wed, 5 Feb 2014 19:06:34 +0000 (+0100) Subject: presentation progress X-Git-Tag: yosys-0.2.0~79 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7e9ba60df88661f1eb9996b802bd5ba6b60a2d73;p=yosys.git presentation progress --- diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex index 74f0e82c8..8457ceb77 100644 --- a/manual/PRESENTATION_ExAdv.tex +++ b/manual/PRESENTATION_ExAdv.tex @@ -24,7 +24,155 @@ This section contains 4 subsections: \subsectionpagesuffix \end{frame} -\subsubsection{TBD} +\subsubsection{Simple selections} + +\begin{frame}[fragile]{\subsubsecname} +Most Yosys commands make use of the ``selection framework'' of Yosys. It can be used +to apply commands only to part of the design. For example: + +\medskip +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +delete # will delete the whole design, but + +delete foobar # will only delete the module foobar. +\end{lstlisting} + +\bigskip +The {\tt select} command can be used to create a selection for subsequent +commands. For example: + +\medskip +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +select foobar # select the module foobar +delete # delete selected objects +select -clear # reset selection (select whole design) +\end{lstlisting} +\end{frame} + +\subsubsection{Selection by object name} + +\begin{frame}[fragile]{\subsubsecname} +The easiest way to select objects is by object name. This is usually only done +in synthesis scripts that are hand-tailored for a specific design. + +\bigskip +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +select foobar # select module foobar +select foo* # select all modules whose names start with foo +select foo*/bar* # select all objects matching bar* from modules matching foo* +select */clk # select objects named clk from all modules +\end{lstlisting} +\end{frame} + +\subsubsection{Module and design context} + +\begin{frame}[fragile]{\subsubsecname} +Commands can be executed in {\it module\/} or {\it design\/} context. Until now all +commands have been executed in design context. The {\tt cd} command can be used +to switch to module context. + +\bigskip +In module context all commands only effect the active module. Objects in the module +are selected without the {\tt /} prefix. For example: + +\bigskip +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +cd foo # switch to module foo +delete bar # delete object foo/bar + +cd mycpu # switch to module mycpu +dump reg_* # print details on all objects whose names start with reg_ + +cd .. # switch back to design +\end{lstlisting} + +\bigskip +Note: Most synthesis script never switch to module context. But it is a very powerful +tool for interactive design investigation. +\end{frame} + +\subsubsection{Selecting by object property or type} + +\begin{frame}[fragile]{\subsubsecname} +Special pattern can be used to select by object property or type. For example: + +\bigskip +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +select w:reg_* # select all wires whose names start with reg_ +select a:foobar # select all objects with the attribute foobar set +select a:foobar=42 # select all objects with the attribute foobar set to 42 +select A:blabla # select all module with the attribute blabla set +select foo/t:$add # select all $add cells from the module foo +\end{lstlisting} + +\bigskip +A complete list of this pattern expressions can be found in the command +reference to the {\tt select} command. +\end{frame} + +\subsubsection{Combining selection} + +\begin{frame}[fragile]{\subsubsecname} +When more than one selection expression is used in one statement they are +pushed on a stack. At the final elements on the stack are combined into a union: + +\medskip +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +select t:$dff r:WIDTH>1 # all cells of type $dff and/or with a parameter WIDTH > 1 +\end{lstlisting} + +\bigskip +Special \%-commands can be used to combine the elements on the stack: + +\medskip +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +select t:$dff r:WIDTH>1 %i # all cells of type $dff *AND* with a parameter WIDTH > 1 +\end{lstlisting} + +\medskip +\begin{block}{Examples for {\tt \%}-codes (see {\tt help select} for full list)} +{\tt \%u} \dotfill union of top two elements on stack -- pop 2, push 1 \\ +{\tt \%d} \dotfill difference of top two elements on stack -- pop 2, push 1 \\ +{\tt \%i} \dotfill intersection of top two elements on stack -- pop 2, push 1 \\ +{\tt \%n} \dotfill inverse of top element on stack -- pop 1, push 1 \\ +\end{block} +\end{frame} + +\subsubsection{Expanding selections} + +\begin{frame}[fragile]{\subsubsecname} +Selections of cells and wires can be expanded along connections using {\tt \%}-codes +for selecting input cones ({\tt \%ci}), output cones ({\tt \%co}), or both ({\tt \%x}). + +\medskip +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +# select all wires that are inputs to $add cells +select t:$add %ci w:* %i +\end{lstlisting} + +\bigskip +Additional constraints such as port names can be specified. + +\medskip +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +# select all wires that connect a "Q" output with a "D" input +select c:* %co:+[Q] w:* %i c:* %ci:+[D] w:* %i %i + +# select the multiplexer tree that drives the signal 'state' +select state %ci*:+$mux,$pmux[A,B,Y] +\end{lstlisting} + +\bigskip +See {\tt help select} for full documentation of this expressions. +\end{frame} + +\subsubsection{Incremental selection} + +\begin{frame}{\subsubsecname} +TBD +\end{frame} + +\subsubsection{Creating selection variables} \begin{frame}{\subsubsecname} TBD diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex index 9aa9bfebc..f84d3537c 100644 --- a/manual/PRESENTATION_ExSyn.tex +++ b/manual/PRESENTATION_ExSyn.tex @@ -31,7 +31,7 @@ \subsection{Reading the design} \begin{frame}[fragile]{\subsecname} -\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] read_verilog file1.v read_verilog -I include_dir -D enable_foo -D WIDTH=12 file2.v read_verilog -lib cell_library.v @@ -59,7 +59,7 @@ connected. It also re-runs the AST parts of the Verilog frontend to create all needed variations of parametric modules. \bigskip -\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] # simplest form. at least this version should be used after reading all input files # hierarchy @@ -87,7 +87,7 @@ multiplexer and register cells. The {\tt proc} command is actually a macro-command that calls the following other commands: -\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] proc_clean # remove empty branches and processes proc_rmdead # remove unreachable branches proc_init # special handling of "initial" blocks @@ -108,7 +108,7 @@ after design elaboration. \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_01.v} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_01.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/proc_01.ys} \end{columns} \hfil\includegraphics[width=8cm,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_01.pdf} \end{frame} @@ -120,7 +120,7 @@ after design elaboration. \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_02.v} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_02.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/proc_02.ys} \end{columns} \end{frame} @@ -129,7 +129,7 @@ after design elaboration. \vskip-1cm \begin{columns} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_03.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/proc_03.ys} \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_03.v} \end{columns} @@ -143,7 +143,7 @@ after design elaboration. The {\tt opt} command implements a series of simple optimizations. It also is a macro command that calls other commands: -\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] opt_const # const folding opt_share -nomux # merging identical cells @@ -160,7 +160,7 @@ while [changed design] The command {\tt clean} can be used as alias for {\tt opt\_clean}. And {\tt ;;} can be used as shortcut for {\tt clean}. For example: -\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] proc; opt; memory; opt_const;; fsm;; \end{lstlisting} \end{frame} @@ -170,7 +170,7 @@ proc; opt; memory; opt_const;; fsm;; \vskip-1cm \begin{columns} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_01.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_01.ys} \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_01.v} \end{columns} @@ -181,7 +181,7 @@ proc; opt; memory; opt_const;; fsm;; \vskip-1cm \begin{columns} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_02.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_02.ys} \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_02.v} \end{columns} @@ -192,7 +192,7 @@ proc; opt; memory; opt_const;; fsm;; \vskip-1cm \begin{columns} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_03.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_03.ys} \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_03.v} \end{columns} @@ -205,7 +205,7 @@ proc; opt; memory; opt_const;; fsm;; \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_04.v} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/opt_04.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_04.ys} \end{columns} \end{frame} @@ -245,7 +245,7 @@ consolidating the number of ports for a memory easier. The {\tt memory} transforms memories to an implementation. Per default that is logic for address decoders and registers. It also is a macro command that calls other commands: -\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] # this merges registers into the memory read- and write cells. memory_dff @@ -262,7 +262,7 @@ memory_map Usually it is preferred to use architecture-specific RAM resources for memory. For example: -\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] memory -nomap; techmap -map my_memory_map.v; memory_map \end{lstlisting} \end{frame} @@ -272,7 +272,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map \vskip-1cm \begin{columns} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/memory_01.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/memory_01.ys} \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/memory_01.v} \end{columns} @@ -285,7 +285,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/memory_02.v} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/memory_02.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/memory_02.ys} \end{columns} \end{frame} @@ -298,7 +298,7 @@ The {\tt fsm} command identifies, extracts, optimizes (re-encodes), and re-synthesizes finite state machines. It again is a macro that calls a series of other commands: -\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] fsm_detect # unless got option -nodetect fsm_extract @@ -357,7 +357,7 @@ verilog source. For example implementing a 32 bit adder using 16 bit adders: }\vbox to 0cm{ \vskip-0.5cm \lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExSyn/techmap_01.v} -\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/techmap_01.ys} +\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/techmap_01.ys} } \end{frame} @@ -413,7 +413,7 @@ more advanced ABC features. It is also possible to write the design with \column[t]{5cm} \lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/abc_01.v} \column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/abc_01.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/abc_01.ys} \end{columns} \includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/abc_01.pdf} \end{frame} @@ -448,7 +448,7 @@ This command inserts this cells to the design. \begin{frame}[fragile]{\subsecname} \begin{columns} \column[t]{4cm} -\begin{lstlisting}[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont] +\begin{lstlisting}[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=ys] # read and elaborate design read_verilog cpu_top.v cpu_ctrl.v cpu_regs.v read_verilog -D WITH_MULT cpu_alu.v diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 1075e3d5a..446574490 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -272,16 +272,16 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des \begin{minipage}[t]{6cm} \tt\scriptsize -\# read design\\ +{\color{YosysGreen}\# read design}\\ \boxalert<1>{read\_verilog counter.v}\\ \boxalert<2>{hierarchy -check -top counter} \medskip -\# the high-level stuff\\ +{\color{YosysGreen}\# the high-level stuff}\\ \boxalert<3>{proc}; \boxalert<4>{opt}; \boxalert<5>{memory}; \boxalert<6>{opt}; \boxalert<7>{fsm}; \boxalert<8>{opt} \medskip -\# mapping to internal cell library\\ +{\color{YosysGreen}\# mapping to internal cell library}\\ \boxalert<9>{techmap}; \boxalert<10>{opt} \bigskip @@ -289,19 +289,19 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des \end{minipage} \begin{minipage}[t]{5cm} \tt\scriptsize -\# mapping flip-flops to mycells.lib\\ +{\color{YosysGreen}\# mapping flip-flops to mycells.lib}\\ \boxalert<11>{dfflibmap -liberty mycells.lib} \medskip -\# mapping logic to mycells.lib\\ +{\color{YosysGreen}\# mapping logic to mycells.lib}\\ \boxalert<12>{abc -liberty mycells.lib} \medskip -\# cleanup\\ +{\color{YosysGreen}\# cleanup}\\ \boxalert<13>{clean} \medskip -\# write synthesized design\\ +{\color{YosysGreen}\# write synthesized design}\\ \boxalert<14>{write\_verilog synth.v} \end{minipage} @@ -428,68 +428,68 @@ Command reference: \bigskip Commands for design navigation and investigation: -\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] - cd a shortcut for 'select -module ' - ls list modules or objects in modules - dump print parts of the design in ilang format - show generate schematics using graphviz - select modify and view the list of selected objects +\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] + cd # a shortcut for 'select -module ' + ls # list modules or objects in modules + dump # print parts of the design in ilang format + show # generate schematics using graphviz + select # modify and view the list of selected objects \end{lstlisting} \bigskip Commands for executing scripts or entering interactive mode: -\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] - shell enter interactive command mode - history show last interactive commands - script execute commands from script file - tcl execute a TCL script file +\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] + shell # enter interactive command mode + history # show last interactive commands + script # execute commands from script file + tcl # execute a TCL script file \end{lstlisting} \end{frame} \begin{frame}[fragile]{\subsecname{} 2/3 \hspace{0pt plus 1 filll} (excerpt)} Commands for reading and elaborating the design: -\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] - read_ilang read modules from ilang file - read_verilog read modules from verilog file - hierarchy check, expand and clean up design hierarchy +\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] + read_ilang # read modules from ilang file + read_verilog # read modules from verilog file + hierarchy # check, expand and clean up design hierarchy \end{lstlisting} \bigskip Commands for high-level synthesis: -\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] - proc translate processes to netlists - fsm extract and optimize finite state machines - memory translate memories to basic cells - opt perform simple optimizations +\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] + proc # translate processes to netlists + fsm # extract and optimize finite state machines + memory # translate memories to basic cells + opt # perform simple optimizations \end{lstlisting} \bigskip Commands for technology mapping: -\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] - techmap simple technology mapper - abc use ABC for technology mapping - dfflibmap technology mapping of flip-flops - hilomap technology mapping of constant hi- and/or lo-drivers - iopadmap technology mapping of i/o pads (or buffers) - flatten flatten design +\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] + techmap # simple technology mapper + abc # use ABC for technology mapping + dfflibmap # technology mapping of flip-flops + hilomap # technology mapping of constant hi- and/or lo-drivers + iopadmap # technology mapping of i/o pads (or buffers) + flatten # flatten design \end{lstlisting} \end{frame} \begin{frame}[fragile]{\subsecname{} 3/3 \hspace{0pt plus 1 filll} (excerpt)} Commands for writing the results: -\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] - write_blif write design to BLIF file - write_btor write design to BTOR file - write_edif write design to EDIF netlist file - write_ilang write design to ilang file - write_spice write design to SPICE netlist file - write_verilog write design to verilog file +\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] + write_blif # write design to BLIF file + write_btor # write design to BTOR file + write_edif # write design to EDIF netlist file + write_ilang # write design to ilang file + write_spice # write design to SPICE netlist file + write_verilog # write design to verilog file \end{lstlisting} \bigskip Script-Commands for standard synthesis tasks: -\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] - synth_xilinx synthesis for Xilinx FPGAs +\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] + synth_xilinx # synthesis for Xilinx FPGAs \end{lstlisting} \bigskip diff --git a/manual/presentation.tex b/manual/presentation.tex index aa26132de..35a409cbe 100644 --- a/manual/presentation.tex +++ b/manual/presentation.tex @@ -1,4 +1,5 @@ \documentclass{beamer} +\hypersetup{bookmarksdepth=5} \usepackage[T1]{fontenc} % required for luximono! \usepackage{lmodern} @@ -52,6 +53,14 @@ morestring=[b]", } +\lstdefinelanguage{ys}{ + morecomment=[l]{\#}, +} + +\lstset{ + commentstyle=\color{YosysGreen}, +} + \newenvironment{boxalertenv}{\begin{altenv}% {\usebeamertemplate{alerted text begin}\usebeamercolor[fg]{alerted text}\usebeamerfont{alerted text}\setlength{\fboxsep}{1pt}\colorbox{bg}} {\usebeamertemplate{alerted text end}}{\color{.}}{}}{\end{altenv}}