From: lkcl <lkcl@web>
Date: Mon, 6 Sep 2021 15:22:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~208
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7eb2cae95ac9bc8b54656a02996c6e763ca29d71;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 6aa54155b..fefe53172 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -129,7 +129,8 @@ Brief description of fields:
 
 * **sz=1** if predication is enabled and `sz=1` and a predicate
   element bit is zero, `SNZ` will
-  be substituted in place of the CR bit selected by `BI`.
+  be substituted in place of the CR bit selected by `BI`,
+  as the Condition tested.
   Contrast this with
   normal SVP64 `sz=1` behaviour, where *only* a zero is put in
   place of masked-out predicate bits.