From: lkcl <lkcl@web>
Date: Sat, 23 Jul 2022 09:38:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1108
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7eb64e9577dd60b6f928ed28c37971478ef08d6a;p=libreriscv.git

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diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
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+
+
+Simple-V is a Scalable Vector ISA Extension specifically for the Power ISA.
+It is extremely important to think of Simple-V as a 2-Dimensional ISA:
+instructions vertical and registers horizontal, otherwise it will be
+difficult to understand.
+
+Simple-V is **not RISC-V and is not RISC-V Vectors**. NEC SX Aurora,
+RVV and Simple-V are all based on Cray-style Vectors hence the similarity,
+the provision of a `setvl` instruction and why they are called
+"Scalable" Vectors because it is the `setvl` instruction that
+presents the programmer with explicit control over Vector length.
+
+ARM NEON, AVX-512 and ARM SVE2 are all Predicated SIMD ISAs and
+**do not provide Scalability**. Programmers must emulate scaling
+through explicit predicate masks which increases instruction count in
+hot-loops.
+
+Links to Simulator and Unit tests:
+
+* Simple-V Simulator