From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 6 Aug 2014 15:51:50 +0000 (+0800)
Subject: mibuild/xilinx: connect CE on reset synchronizer FFs
X-Git-Tag: 24jan2021_ls180~2099^2~326
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ebf08db5ea1904ca22e6bb3fd4d8fc2a21b6c7f;p=litex.git

mibuild/xilinx: connect CE on reset synchronizer FFs
---

diff --git a/mibuild/xilinx_common.py b/mibuild/xilinx_common.py
index dbd3decd..1d3c5800 100644
--- a/mibuild/xilinx_common.py
+++ b/mibuild/xilinx_common.py
@@ -72,9 +72,9 @@ class XilinxAsyncResetSynchronizerImpl(Module):
 		rst1 = Signal()
 		self.specials += [
 			Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
-				i_C=cd.clk, o_Q=rst1),
+				i_CE=1, i_C=cd.clk, o_Q=rst1),
 			Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset,
-				i_C=cd.clk, o_Q=cd.rst)
+				i_CE=1, i_C=cd.clk, o_Q=cd.rst)
 		]
 
 class XilinxAsyncResetSynchronizer: