From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 17:13:52 +0000 (+0000)
Subject: opt_lut: leave intact LUTs with cascade feeding module outputs.
X-Git-Tag: yosys-0.9~390^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ec740b7ad4ee4bc02e2564671e0153cdd08152f;p=yosys.git

opt_lut: leave intact LUTs with cascade feeding module outputs.
---

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 4207fbdb9..ba2cc6ee7 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -225,6 +225,12 @@ struct OptLutWorker
 
 					log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
 
+					if (index.query_is_output(lutA->getPort("\\Y")))
+					{
+						log("  Not combining LUTs (cascade connection feeds module output).\n");
+						continue;
+					}
+
 					pool<SigBit> lutA_inputs;
 					pool<SigBit> lutB_inputs;
 					for (auto &bit : lutA_input)
diff --git a/tests/opt/opt_lut_port.il b/tests/opt/opt_lut_port.il
new file mode 100644
index 000000000..7eb71890f
--- /dev/null
+++ b/tests/opt/opt_lut_port.il
@@ -0,0 +1,18 @@
+module $1
+  wire width 4 input 2 \_0_
+  wire output 4 \_1_
+  wire input 3 \_2_
+  wire output 1 \o
+  cell $lut \_3_
+    parameter \LUT 16'0011000000000011
+    parameter \WIDTH 4
+    connect \A { \_0_ [3] \o 2'00 }
+    connect \Y \_1_
+  end
+  cell $lut \_4_
+    parameter \LUT 4'0001
+    parameter \WIDTH 4
+    connect \A { 3'000 \_2_ }
+    connect \Y \o
+  end
+end
diff --git a/tests/opt/opt_lut_port.ys b/tests/opt/opt_lut_port.ys
new file mode 100644
index 000000000..51dfd988b
--- /dev/null
+++ b/tests/opt/opt_lut_port.ys
@@ -0,0 +1,2 @@
+read_ilang opt_lut_port.il
+select -assert-count 2 t:$lut