From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 14 Nov 2015 21:04:33 +0000 (+0100)
Subject: soc/integration/cpu_interface: add bases, constants and memories output to csv files
X-Git-Tag: 24jan2021_ls180~2060
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ed2576ce1e09709f75118b5a763bc21c611f6ed;p=litex.git

soc/integration/cpu_interface: add bases, constants and memories output to csv files
---

diff --git a/litex/soc/cores/uart/software/csr.py b/litex/soc/cores/uart/software/csr.py
new file mode 100644
index 00000000..0cf706d0
--- /dev/null
+++ b/litex/soc/cores/uart/software/csr.py
@@ -0,0 +1,78 @@
+import csv
+
+# TODO: move
+
+class MappedReg:
+    def __init__(self, readfn, writefn, name, addr, length, busword, mode):
+        self.readfn = readfn
+        self.writefn = writefn
+        self.addr = addr
+        self.length = length
+        self.busword = busword
+        self.mode = mode
+
+    def read(self):
+        if self.mode not in ["rw", "ro"]:
+            raise KeyError(name + "register not readable")
+        datas = self.readfn(self.addr, burst_length=self.length)
+        if isinstance(datas, int):
+            return datas
+        else:
+            data = 0
+            for i in range(self.length):
+                data = data << self.busword
+                data |= datas[i]
+            return data
+
+    def write(self, value):
+        if self.mode not in ["rw", "wo"]:
+            raise KeyError(name + "register not writable")
+        datas = []
+        for i in range(self.length):
+            datas.append((value >> ((self.length-1-i)*self.busword)) & (2**self.busword-1))
+        self.writefn(self.addr, datas)
+
+
+class MappedElements:
+    def __init__(self, d):
+        self.d = d
+
+    def __getattr__(self, attr):
+        try:
+            return self.__dict__['d'][attr]
+        except KeyError:
+            pass
+        raise KeyError("No such element " + attr)
+
+
+def build_csr_bases(addrmap):
+    csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
+    d = {}
+    for item in csv_reader:
+        group, name, addr, dummy0, dummy1 = item
+        if group == "csr_base":
+            d[name] = int(addr.replace("0x", ""), 16)
+    return MappedElements(d)
+
+def build_csr_registers(addrmap, busword, readfn, writefn):
+    csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
+    d = {}
+    for item in csv_reader:
+        group, name, addr, length, mode = item
+        if group == "csr_register":
+            addr = int(addr.replace("0x", ""), 16)
+            length = int(length)
+            d[name] = MappedReg(readfn, writefn, name, addr, length, busword, mode)
+    return MappedElements(d)
+
+def build_constants(addrmap):
+    csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
+    d = {}
+    for item in csv_reader:
+        group, name, value, dummy0, dummy1 = item
+        if group == "constant":
+            try:
+                d[name] = int(value)
+            except:
+                d[name] = value
+    return MappedElements(d)
diff --git a/litex/soc/cores/uart/software/reg.py b/litex/soc/cores/uart/software/reg.py
deleted file mode 100644
index 6f154fd7..00000000
--- a/litex/soc/cores/uart/software/reg.py
+++ /dev/null
@@ -1,56 +0,0 @@
-import csv
-
-# TODO: share reg for all software drivers
-
-class MappedReg:
-    def __init__(self, readfn, writefn, name, addr, length, busword, mode):
-        self.readfn = readfn
-        self.writefn = writefn
-        self.addr = addr
-        self.length = length
-        self.busword = busword
-        self.mode = mode
-
-    def read(self):
-        if self.mode not in ["rw", "ro"]:
-            raise KeyError(name + "register not readable")
-        datas = self.readfn(self.addr, burst_length=self.length)
-        if isinstance(datas, int):
-            return datas
-        else:
-            data = 0
-            for i in range(self.length):
-                data = data << self.busword
-                data |= datas[i]
-            return data
-
-    def write(self, value):
-        if self.mode not in ["rw", "wo"]:
-            raise KeyError(name + "register not writable")
-        datas = []
-        for i in range(self.length):
-            datas.append((value >> ((self.length-1-i)*self.busword)) & (2**self.busword-1))
-        self.writefn(self.addr, datas)
-
-
-class MappedRegs:
-    def __init__(self, d):
-        self.d = d
-
-    def __getattr__(self, attr):
-        try:
-            return self.__dict__['d'][attr]
-        except KeyError:
-            pass
-        raise KeyError("No such register " + attr)
-
-
-def build_map(addrmap, busword, readfn, writefn):
-    csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
-    d = {}
-    for item in csv_reader:
-        name, addr, length, mode = item
-        addr = int(addr.replace("0x", ""), 16)
-        length = int(length)
-        d[name] = MappedReg(readfn, writefn, name, addr, length, busword, mode)
-    return MappedRegs(d)
diff --git a/litex/soc/cores/uart/software/wishbone.py b/litex/soc/cores/uart/software/wishbone.py
index 82723adb..8e9e7fcf 100644
--- a/litex/soc/cores/uart/software/wishbone.py
+++ b/litex/soc/cores/uart/software/wishbone.py
@@ -1,8 +1,7 @@
 import serial
 from struct import *
 
-# TODO: share reg for all software drivers
-from litex.soc.cores.uart.software.reg import *
+from litex.soc.cores.uart.software.csr import *
 
 
 def write_b(uart, data):
@@ -20,7 +19,9 @@ class UARTWishboneBridgeDriver:
         self.debug = debug
         self.uart = serial.Serial(port, baudrate, timeout=0.25)
         if addrmap is not None:
-            self.regs = build_map(addrmap, busword, self.read, self.write)
+            self.bases = build_csr_bases(addrmap)
+            self.regs = build_csr_registers(addrmap, busword, self.read, self.write)
+            self.constants = build_constants(addrmap)
 
     def open(self):
         self.uart.flushOutput()
diff --git a/litex/soc/integration/cpu_interface.py b/litex/soc/integration/cpu_interface.py
index 4648b1b8..631cadb2 100644
--- a/litex/soc/integration/cpu_interface.py
+++ b/litex/soc/integration/cpu_interface.py
@@ -114,12 +114,26 @@ def get_csr_header(regions, constants, with_access_functions=True):
     return r
 
 
-def get_csr_csv(regions):
+def get_csr_csv(csr_regions=None, constants=None, memory_regions=None):
     r = ""
-    for name, origin, busword, obj in regions:
-        if not isinstance(obj, Memory):
-            for csr in obj:
-                nr = (csr.size + busword - 1)//busword
-                r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
-                origin += 4*nr
+
+    if csr_regions is not None:
+        for name, origin, busword, obj in csr_regions:
+            r += "csr_base,{},0x{:08x},,\n".format(name, origin)
+
+        for name, origin, busword, obj in csr_regions:
+            if not isinstance(obj, Memory):
+                for csr in obj:
+                    nr = (csr.size + busword - 1)//busword
+                    r += "csr_register,{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
+                    origin += 4*nr
+
+    if constants is not None:
+        for name, value in constants:
+            r += "constant,{},{},,\n".format(name.lower(), value)
+
+    if memory_regions is not None:
+        for name, origin, length in memory_regions:
+            r += "memory_region,{},0x{:08x},{:d},\n".format(name.lower(), origin, length)
+
     return r