From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 14 Dec 2020 06:35:35 +0000 (+0000)
Subject: use insn-histogram analysed set of regs
X-Git-Tag: convert-csv-opcode-to-binary~1326
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ed66c600da864e0d704fb56dcfc29be417e5a21;p=libreriscv.git

use insn-histogram analysed set of regs
---

diff --git a/openpower/sv/comp16-v1-skel.py b/openpower/sv/comp16-v1-skel.py
index 3f56dcdc6..db281796a 100644
--- a/openpower/sv/comp16-v1-skel.py
+++ b/openpower/sv/comp16-v1-skel.py
@@ -179,10 +179,11 @@ def crbtcnd(mop):
 # (remember to exclude nop - ori r0,r0,0 as this skews numbers)
 # Registers representable in a made-up 3-bit mapping.
 # It must contain 0 for proper working of at least storex.
-cregs3 = { 0, 31, 1, 2, 3, 4, 5, 6, 7 }
+#cregs3 = { 0, 31, 1, 2, 3, 4, 5, 6, 7 }
+cregs3 = { 0, 9, 3, 1, 2, 31, 10, 30, 4 }
 # Ditto in a 2-bit mapping.  It needs not contain 0, but it must be a
 # subset of cregs3 for proper working of at least storex.
-cregs2 = { 2, 3, 4, 5 }
+cregs2 = { 9, 3, 1, 2 }
 # Use the same sets for FP for now.
 cfregs3 = cregs3
 cfregs2 = cregs2