From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Sep 2021 12:24:55 +0000 (+0100)
Subject: redo SVP64 RM Decode to new CTR-Test Mode (svstep not included)
X-Git-Tag: xlen-bcd~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ed8695c03d096024cea6d9c07630238ed9036d4;p=openpower-isa.git

redo SVP64 RM Decode to new CTR-Test Mode (svstep not included)
---

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index 934b4389..42788d5f 100644
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -230,7 +230,7 @@ class SVP64MODEb:
     BC_SNZ = 3  # for branch-conditional mode
     BC_VLI = 2  # for VL include/exclude on VLSET mode
     BC_VLSET = 1 # VLSET mode
-    BC_SVSTEP = 0 # svstep mode
+    BC_CTRTEST = 0 # CTR-test mode
     # reduce mode
     REDUCE = 2  # 0=normal predication 1=reduce mode
     PARALLEL = 3 # 1=parallel reduce, 0=scalar reduce
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index eee86b94..db854396 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -210,11 +210,10 @@ class SVP64BCGate(Enum):
     ALL = 1
 
 
-@unique
-class SVP64BCStep(Enum):
+class SVP64BCCTRMode(Enum):
     NONE = 0
-    STEP = 1
-    STEP_RC = 2
+    TEST = 1
+    TEST_INV = 2
 
 
 @unique
diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 81527ad5..02c459bc 100644
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -20,7 +20,7 @@ from nmigen import Elaboratable, Module, Signal, Const
 from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
                                     SVP64PredMode, SVP64sat, SVP64LDSTmode,
                                     SVP64BCPredMode, SVP64BCVLSETMode,
-                                    SVP64BCGate, SVP64BCStep,
+                                    SVP64BCGate, SVP64BCCTRMode,
                                     )
 from openpower.consts import EXTRA3, SVP64MODE
 from openpower.sv.svp64 import SVP64Rec
@@ -105,7 +105,7 @@ class SVP64RMModeDecode(Elaboratable):
 
         # Branch Conditional Modes
         self.bc_vlset = Signal(SVP64BCVLSETMode) # Branch-Conditional VLSET
-        self.bc_step = Signal(SVP64BCStep)   # Branch-Conditional svstep mode
+        self.bc_ctrtest = Signal(SVP64BCCTRMode) # Branch-Conditional CTR-Test
         self.bc_pred = Signal(SVP64BCPredMode) # BC predicate mode
         self.bc_vsb = Signal()                 # BC VLSET-branch (like BO[1])
         self.bc_gate = Signal(SVP64BCGate)     # BC ALL or ANY gate
@@ -141,12 +141,12 @@ class SVP64RMModeDecode(Elaboratable):
 
         with m.If(is_bc):
             # Branch-Conditional is completely different
-            # svstep mode
-            with m.If(mode[SVP64MODE.BC_SVSTEP]):
+            # Counter-Test Mode.
+            with m.If(mode[SVP64MODE.BC_CTRTEST]):
                 with m.If(self.rm_in.ewsrc[0]):
-                    comb += self.bc_step.eq(SVP64BCStep.STEP_RC)
+                    comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST_INV)
                 with m.Else():
-                    comb += self.bc_step.eq(SVP64BCStep.STEP)
+                    comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST)
             # VLSET mode
             with m.If(mode[SVP64MODE.BC_VLSET]):
                 with m.If(mode[SVP64MODE.BC_VLI]):