From: Staf Verhaegen Date: Fri, 8 May 2020 19:08:50 +0000 (+0200) Subject: Re: [libre-riscv-dev] minimum viable ASIC X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7eda635aab8307bfdad7f2290fe70290cfbfe77c;p=libre-riscv-dev.git Re: [libre-riscv-dev] minimum viable ASIC --- diff --git a/9b/5899f270250200276f45da64e6957ac3eefd72 b/9b/5899f270250200276f45da64e6957ac3eefd72 new file mode 100644 index 0000000..190d507 --- /dev/null +++ b/9b/5899f270250200276f45da64e6957ac3eefd72 @@ -0,0 +1,99 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Fri, 08 May 2020 20:08:58 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jX8Mj-0002IR-SA; Fri, 08 May 2020 20:08:57 +0100 +Received: from vps2.stafverhaegen.be ([85.10.201.15]) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) id 1jX8Mi-0002IK-9g + for libre-riscv-dev@lists.libre-riscv.org; Fri, 08 May 2020 20:08:56 +0100 +Received: from hpdc7800 (hpdc7800 [10.0.0.1]) + by vps2.stafverhaegen.be (Postfix) with ESMTP id B0A9311C05B7 + for ; + Fri, 8 May 2020 21:08:55 +0200 (CEST) +Message-ID: <8a9513e929732def9055bf6ec09da2deeea3f794.camel@fibraservi.eu> +From: Staf Verhaegen +To: libre-riscv-dev@lists.libre-riscv.org +Date: Fri, 08 May 2020 21:08:50 +0200 +In-Reply-To: +References: + <7fcce2dc2715c268c1029783a83ebcd814c489b9.camel@fibraservi.eu> + <7E85F682-C471-4B1D-882A-8E7B54021E18@gatech.edu> + +Organization: FibraServi bvba +X-Mailer: Evolution 3.28.5 (3.28.5-8.el7) +Mime-Version: 1.0 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] minimum viable ASIC +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============5275800997008115847==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============5275800997008115847== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-6U6722RD5QNhbDV6+d+q" + + +--=-6U6722RD5QNhbDV6+d+q +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + +Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 13:46 [+0100]: +> On Fri, May 8, 2020 at 1:44 PM Yehowshua wrote: +> > I talked to Raptor and if Series A doesn=E2=80=99t pan out in August, R= +aptor is willing to foot 30k for PLL design in exchange for some equity. +>=20 +> that's fantastic. it would give us (and any other team)Foundry-independe= +nce. normally the PLL is available as a StandardCell from a Foundry... but= + only under NDA. + +Be aware that PLL is an analog block meaning that if you let it design for = +a certain process from a certain foundry it will only work for that node an= +d foundry. It is not portable like RTL code is unless specifically designed= + for that but analog designers typically don't know how to do that. Also in= + order to design the PLL you need NDA to access the PDK which likely also f= +orbids making the final GDSII of your design public. + +Also giving away equity gives cause for other type of dependence... + +greets, +Staf. + + + +--=-6U6722RD5QNhbDV6+d+q-- + + + +--===============5275800997008115847== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============5275800997008115847==-- + + +