From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 27 May 2022 08:23:34 +0000 (+0200)
Subject: Use proper operator
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ee570a75e876e0e7d73ad2ee54a0be92956c03d;p=yosys.git

Use proper operator
---

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 85c44824f..76ba77abb 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -729,12 +729,12 @@ struct FirrtlWorker
 					always_uint = true;
 					firrtl_width = max(a_width, b_width);
 				}
-				else if ((cell->type == ID($eq)) | (cell->type == ID($eqx))) {
+				else if ((cell->type == ID($eq)) || (cell->type == ID($eqx))) {
 					primop = "eq";
 					always_uint = true;
 					firrtl_width = 1;
 				}
-				else if ((cell->type == ID($ne)) | (cell->type == ID($nex))) {
+				else if ((cell->type == ID($ne)) || (cell->type == ID($nex))) {
 					primop = "neq";
 					always_uint = true;
 					firrtl_width = 1;
@@ -759,7 +759,7 @@ struct FirrtlWorker
 					always_uint = true;
 					firrtl_width = 1;
 				}
-				else if ((cell->type == ID($shl)) | (cell->type == ID($sshl))) {
+				else if ((cell->type == ID($shl)) || (cell->type == ID($sshl))) {
 					// FIRRTL will widen the result (y) by the amount of the shift.
 					// We'll need to offset this by extracting the un-widened portion as Verilog would do.
 					extract_y_bits = true;
@@ -777,7 +777,7 @@ struct FirrtlWorker
 						firrtl_width = a_width + (1 << b_width) - 1;
 					}
 				}
-				else if ((cell->type == ID($shr)) | (cell->type == ID($sshr))) {
+				else if ((cell->type == ID($shr)) || (cell->type == ID($sshr))) {
 					// We don't need to extract a specific range of bits.
 					extract_y_bits = false;
 					// Is the shift amount constant?